Company Contact: Jim Bridges (610) 776-6669
VMEbus Mezzanine Card Features Two IDT R3081s
February 6, 1995. Allentown, PA. Communication Automation & Control, Inc. announces a VMEbus mezzanine board with a pair of 40-MHz IDT R3081 RISC processors. Dubbed the 6U3081, the board features a peak performance of 70 MIPS and 22 MFLOPS. Each processor on the board is equipped with one Mbyte of private zero-wait-state SRAM. The two processors also share either two or eight Mbytes of global DRAM. A pair of RS-232C UARTs provide shared serial I/O for the two processors.
The 6U3081 is designed for use with CAC's 150-MFLOPS, 75-MIPS VME6U6 VMEbus digital signal processing board. Based on six 50-MHz AT&T DSP32C floating point DSPs, the board features 512 kbytes of private zero-wait-state SRAM per DSP and a full master/slave VMEbus interface. The mezzanine interface between the VME6U6 and 6U3081 consists of four 16-Mbit/sec TDM (Time Division Multiplexed) buses, which are also used as a local bus to interconnect the VME6U6's six DSP32Cs.
Time division multiplexing enables each TDM bus to carry data to and from multiple DSPs and MIPS processors simultaneously. The bandwidth for each bus is allocated using programmable time slots. Designers specify connections between DSPs, MIPS processors, and other mezzanine devices (such as Codecs) on a slot by slot basis by filling out a table known as a TDM map, which is compiled and downloaded to the DSP board.
In addition to the 6U3081, CAC offers a number of other TDM mezzanine cards for the VME6U6. Among these are a T1 interface, a Codec card with twelve 8-bit companding Codecs, and a variety of high-resolution, multi-channel audio cards. All of these mezzanine cards use the same TDM interface as that used on the 6U3081.
Software development support for the 6U3081 includes Sun/Unix-hosted versions of BSO's (Boston Systems Office) C compiler, assembler, and source-level debugger. These tools work in conjunction with CAC's host library, which enables the host to control the MIPS processors and transfer data/programs between the host and MIPS processor memory.
The 6U3081 also comes equipped with a real-time operating system. Developed by Woodward McCoach, Inc. the multitasking RTOS provides a fully protected operating environment with support for both priority and time-sliced process scheduling.
The MIPS 3081 processors access the host file system by making common Unix system calls such as open, read, and write, and invoking standard C library functions such as fopen and fprintf. A daemon background process running on the host provides the interface between the MIPS kernel and host operating system. The two MIPS processors can share data through global memory using Unix-like shared memory functions. Interprocessor communications between MIPS, DSP32C, and host processes are provided through a Unix-like socket library. Routines are also provided for interrupt driven I/O.
The 6U3081 costs $5000 and is available immediately.
For further information, contact:
Communication
Automation and Control
1642 Union Blvd. Ste. 200
Allentown, PA 18103-1510
Tel: (610) 776-6669
Fax: (610) 770-1232
Email: sales@cacdsp.com