QuicKit Telephony - 6QH5420A

The modular design of our QuicKit^TM architecture makes it possible to rapidly prototype high-performance DSP and telecom boards that meet customer requirements.The 6QH5420A is a 6U hot swap VME board configured as the most powerful single board solution for processing ATM traffic. It consists of our 6U VME baseboard populated with six smPCI Modules.

• 6U hot-swap VME64X baseboard (V6M6HS)
• ATM-OC3 ethernet interface (IMATM)
• 300MHz MIPS RISC R7000 (PM7000)
• 48 ‘C5420 DSPs (DM5420)
• Sun and Intel Solaris API library
• AAL1 and AAL2 protocol software

QuicKit for ATM Developers

VME Hot Swap Baseboard (V6M6HS)

The V6M6HS baseboard features a VME master/slave interface, global DRAM, a local 100 Mbyte/sec PCI bus, four TDM serial buses and six smPCI. Hot swap capability allows the V6M6HS to be inserted into or removed from a live powered backplane without damage to the board, the backplane, or other VME activity.

• On-board 100MHz MIPS RISC processor

• 32MB cronus DRAM (expandable to 128MB)is accessible by all smPCI modules and serves as the local memory for the on-board MIPS processor.

• 32MB (optional flash memory up to 128MB) "NAND" flash memory array holds executables for DSP and/or MIPS processor modules to enable the V6M6HS assembly to be completely self-booting for stand alone operation.

• Four TDM (Time Division Multiplexed) serial buses for inter-module, inter-board communications.

• 16 MB PCI global SDRAM

• H.110 interface connection to an industry standard TDM telephony bus on the VME P2 connector allows up to 512 bi-directional time slots of TDM traffic to flow in and out of the board.

ATM-OC3 (IMATM)

The IMATM module provides an interface between an ATM OC-3 optical link and the PCI bus of our VME baseboard. It includes an optical transceiver, a PHY chip, a SAR chip and associated timing components. It supports hardware-level filtering of ATM cells based on Virtual Circuit and performs autonomous AAL3/4 and AAL5 processing. AAL1 and AAL2 require assistance from the PM7000 RISC processor module.

Optical Transceiver

The IMATM’s transceiver is made up of an HP optical transmitter and receiver, both of which protrude through the front panel of the cover plate. They accommodate SC-type fiber optic connectors and are intended for use with 1300nm multimode fiber.

PHY and Timing Components

A PMC Sierra SUNI-ULTRA chip provides PHY functions including optical transceiver interface, clock recovery, SONET and ATM framing, and UTOPIA interface.

SAR

An IDT77252 NICStAR chip provides ATM cell processing functions. It transmits and receives ATM cells with the PHY via a UTOPIA interface and interfaces to the baseboard via its PCI interface. The IMATM has bus-mastering capabilities that gives the SAR direct access to PCI memory to deposit and retrieve cells and packets of data. This allows long bursts of traffic at full OC-3 rate. The SAR handles all required details of segmentation and reassembly for AAL3/4 and AAL5 packets. Other types of traffic (e.g. AAL1 and AAL2) are treated as raw cells by the SAR and are placed or taken from queues in PCI memory.

RM7000A RISC Processor (PM7000)

Featuring the highest performance embedded MIPS processor available today, the PM7000 module includes a QED (PMC-Sierra) RM7000A 64-bit floating-point microprocessor and 64MB of SDRAM. This RISC processor initializes the PHY and SAR of the IMATM, manages the flow of ATM traffic and handles exception conditions. The RM7000A processor can execute two instructions per clock, so the currently available 350MHz devices yield a peak instruction rate of 700 MIPS. It includes 16KB primary instruction and data caches, plus a 256KB internal secondary cache.

The RM7000A processor is a 64-bit floating-point microprocessor. The chip features:

• pipelined floating-point ALU
• separate integer and floating-point ALUs eliminates dependent latencies
• floating-point multiply-add/subtract instructions
• low-latency multiply-add and conditional move instructions
• single cycle repeat instruction
• two-way set associative cache increases hit rate

The module is a PCI bus master and target. This makes the module’s memory available to other PCI masters, as well as enabling the RM7000A processor to reach any PCI-accessible memory on the baseboard or on other modules. The PCI master logic includes a DMA controller to support memory-to-memory copies with low CPU overhead. The module comes with an optional RS232 connector for debugging purposes.

In addition to the 64MB of on-board local SDRAM, the PM7000 module provides a PCI bus master enabling it to access the carrier board's global memory as well as other modules. Inter-module isochronous communications are accomplished via the TDM buses.

'C5420 DSPs (DM5420)

The micro-BGA package of the dual-core DSP TMS320VC5420 sets the pace for packing density. Our 6QH5420A board offers 48 DSP’s (96 DSP cores) on a 6U VME board. Each DSP core runs at 100 MIPS and includes 100k words of internal program/data memory. The board is rated at 9600 DSP MIPS. The DSPs are packaged 12 to each of four smPCI^TMModules in our DM5420. Each module features:

The Host Port Interface(HPI)

The HPI provides access from a PCI bus bridge to the DSP's internal memory. The module extends the normally passive HPI Bus capability to allow DSPs to request DMA transfers on the HPI bus between DSP internal memory and any PCI-accessible resource.

Shared SDRAM Memory

In addition to the 100K words of internal memory for each DSP core, the module includes 8MB of shared SDRAM. This memory may be accessed from the PCI bus or via DSP-requested DMA transfers between DSP internal RAM and SDRAM via the HPI bus.

JTAG Emulator Port

The DM5420 may be ordered with a JTAG emulator connector. This JTAG port connects to the 24 DSPs in series to support debugging with an external emulator.

The TDM Interface

V6M6 TDM serial data, such as data to/from H.110 interface, is accessed through the multi-channel buffered serial ports (McBSP) of the ‘C5420s. The 24 DSP cores per smPCI module share three common input and three common output McBSP buses. Timeslots on these buses are connected to timeslots on the V6M6HS TDM buses as directed by the TDM controller on the baseboard.

QuicKit Software

Host Computer

The 6QH5420A is supported on Power PC Sparc machines running Solaris.

AAL1/AAL2 Software

Software support for ATM Adaption Layers type 1 (AAL1) and type 2 (AAL2) is available for a MIPS processor (base board MIPS or PM4700, PM5000 or PM7000 smPCI modules) or a ‘C54x DSP module (DM12C549 or DM5420). The AAL2 software also provides extended packets conforming to ITU-T I.366.1 "Segmentation and Reassembly Service Specific Convergence Sublayer for the AAL type 2".

RTEMS Operating System Software

The kernal running on the RM7000A RISC processor is the open software source, real time Operating System, RTEMS. Unless the 6QH5420A board is operating in a self-booting standalone mode, RTEMS requires support from a server process running on the host computer. At this time, only Solaris is supported. RTEMS is available for download free of charge from the On-Line Applications Research Corporation (OAR) web site at www.oarcorp.com.

API Libraries

CAC includes, at no additional cost, software and documentation for the Application Programming Interface libraries. In addition, we include Power-On-Self-Test and diagnostic software.

Customer Support

With our QuicKit System Package^TM, we provide direct, engineer to engineer contact for problem resolution by email or telephone.