6U4T1

This VME6U6 mezzanine board interfaces to four independent T1 lines. For unusual T1 environments in which the in-bound spans are not locked to a common timing source, the circuitry automatically locks to the fastest receive clock to ensure no data loss. Instead, data is duplicated on the TDM bus for slips on the slower lines, which the receiving DSPs ignore. An AMI electrical interface is supported. The TDM clock rate must be 8.192MHz. A special TDM expansion port performs rate conversion to 2.048 or 4.096MHz for up to 64 selected T1 data channels.

Power requirements:1.6A @ 5v