CMXCV

The CMXCV is an multi-purpose user configurable Field Programmable Gate Array module, which allows a programmer to write their own FPGA code to be downloaded in conjunction with the CAC code to the Xilinx FPGA populated on the module.

The heart of the CMXCV module is a Xilinx FPGA from the Virtex-E family. The CMXCV supports three different Xilinx FPGAs from this family. They are the:

• XCV600EFG680 with 600,000 gates,
• XCV1000EFG680 with 1 million gates, and
• XCV2000EFG680 with 2 million gates.

The FPGA connects to the PCI Bus,the TDM Bus, memory, LEDs, and JTAG configuration signals. An 80 pin connector provides 54 bi-directional signals or 27 differential pairs for front panel access or connection to the VME P2 on the V6M6 hot-swap base board; or compactPCI C6M6 base board J3 and J5 slots.

The CMXCV is not 5 volt signaling tolerant. It may not be used with the non-hotswap VME base board or with any other board which is also populated with smPCI modules that require 5 volt signaling, including the IM2T1, IM2E1, IMATM, IMG726, IMHC4, IMHDLC, DM2C31, or DM4C51.

The Virtex-E runs at four primary clock frequencies. They are the PCI clock, the TDM clock, an 80 MHz clock used to drive the memory controllers, and a fourth clock which can be defined by the user.

Each CMXCV module contains two types of memory, SDRAM and 512 kb of fast asynchronous SRAM, which are mapped into the memory space of the PCI Bus and are controlled by the FPGA. The SDRAM is mapped into two 64 MB banks.

In addition to the PCI clock and the TDM clock provided by the baseboard, two other clocks are supplied to the Xilinx FPGA. One clock is set to 80 MHz to control the SDRAM and its controller in the FPGA and the other clock is user programable.

The Xilinx FPGA is configured using the JTAG via the baseboard. The FPGA can also be isolated from the JTAG chain and configured directly by an external source connected to a JTAG header built into the CMXCV board. In addition to allowing for external configuration, this isolation technique allows the customer to use certain Xilinx tools which aid in the design of the FPGA code. One of these tools is Xilinx’s ChipScope, an internal logic analyzer that is placed within the Xilinx FPGA.

There are two LEDs on the cPCI and VME64X baseboards for each CMXCV module.

Control of these LEDs takes place in a PCI Configuration Register. For versatility, this register allows either software or the customer’s hardware to control the signals connected to the baseboard.

The PCI interface provides target read and write access to the SDRAM, SRAM, and USER Space from the PCI bus. All reads and writes pass through internal block rams that are loaded within the Xilinx FPGA.

The CMXCV module supports both single and burst PCI accesses. 8-bit, 16-bit, and 32-bit access are supported for single access mode and 32-bit is supported for burst access mode.

Direct Memory Access(DMA) Controller, provides initiator read and write accesses to the SDRAM, SRAM, and USER Space in addition to accesses between individual on-board memory locations. These transfers also pass through block rams loaded within the FPGA. All DMA transfers are 32-bit accesses.

The CMXCV also supports Configuration Space accesses. The CMXCV does not support target IO Space PCI accesses but does support initiator IO Space accesses.

The 4 TDM buses provides the CMXCV module with a communication channel separate from the PCI bus. TDM communication provides low latency, isochronous data transfers without burdening the local PCI bus. The CMXCV TDM controller provides serial interface to all four TDM data and valid buses.

The CMXCV smPCI module simplifies the process and dramatically reduces the time for a user to complete the loading and testing of user defined software into the Xilinx FPGA. The FPGA code provided by CAC takes care of all PCI bus operations, interfacing with the on-board memory (SDRAM and SRAM), and interfacing with the TDM bus so that the programmer may concentrate on their particular design and not the backbone functionality of the CMXCV. Software provided by CAC is also included to control the FPGA code.

Specifications

Processors	XCV600E
P/N code	MPF1
EEPROM Clock (MHz)	80
User defined Clock (MHz)	Varies
Internal SRAM (kb)	512kB
Ext. SDRAM	128 MB
MTBF (kHr)	N/A
+1.8v power (A)	N/A
+3.3v power (A)	N/A
Max per VME64X	6
6U VME64X sites	any
Max per cPCI	6
6U cPCI sites	any
Size (inches)	2.9 x 2.75

Product Brochure
in PDF format.


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