DM5420

Our DM5420 smPCI module offers up to 144 DSP cores on a 6U VME or 6U CompactPCI baseboard, and 48 DSP cores on the Desktop PCI baseboard.

DM5420 smPCI Module

Each DM5420 module is populated with 12 of these chips; each chip includes two independent DSPs; each DSP core runs at 100 MIPS and includes 100K words of internal program/data memory. The DM5420 thus provides 24 DSP cores, with a total of 2400 MIPS. Our 6U VME V6M6 or V6M6 Hot-swap base boards and our 6U Compact PCI C6M6 base board loaded with six DM5420 modules peaks at 14400 MIPS. Our Desktop PCI bus DPT4 card peaks at 4800 MIPS.

Host Port Interface

All data traffic between the PCI bus of our baseboard and a DSP passes through the host port interface (HPI) of that DSP. The HPI provides access from a PCI bus bridge to the DSP's internal memory.

The HPI bus on a DSP is normally a passive interface that responds to data transfers initiated elsewhere on the PCI bus. The DM5420 extends this capability to allow DSPs to request DMA transfers on the HPI bus between DSP internal memory and any PCI-accessible resource.

Shared SDRAM Memory

In addition to the 100K words of internal memory for each DSP core, the DM5420 includes 8MB of shared SDRAM. This memory may be accessed from the PCI bus or via DSP-requested DMA transfers between DSP internal RAM and SDRAM via the HPI bus.

DSP Synchronization

External interrupt signals 1 and 3 of all 12 DSPs are connected together. These signals allow all DSPs to synchronize to an external source, such as TDM superframe, TDM frame, or other interrupt source.

Module FPGA

The DM5420 module uses a Xilinx XC4044XLA to interface the DSPs with the SDRAM and the local PCI and TDM buses.

JTAG Emulator Port

The DM5420 may be ordered with a JTAG emulator connector. This JTAG port connects to the 24 DSPs in series to support debugging with an external emulator. When so equipped, the DM5420 may only be installed in module sites A or C of the 6U VME or 6U Compact PCI baseboard in order to gain access to the JTAG connector through the front panel.

TDM Interface

TDM serial data, such as data to/from H.110 or T1/E1 interfaces, is accessed through the multi-channel buffered serial ports (McBSP) of the ‘5420s. The 24 DSPs share three common input and three common output McBSP buses. Timeslots on these buses are connected to timeslots on the four TDM buses as directed by the TDM controller on the baseboard. Coordination of McBSP timeslot usage among the 24 DSPs on a DM5420 is distributed to those DSPs.

Specifications

Product Brochure
in PDF format.