DM5441

Our DM5441 provides 16 DSP cores per module, with a total of 2128 DSP Mips per module. The micro-BGA packaging of the DSP TMS320VC5441 now sets the pace for packing density. Our DM5441 PCI module offers up to 96 DSP cores on a 6U VME or 6U Compact PCI baseboard.

DM5441 smPCI Module

Each module is populated with 4 of these TI 'C5441 chips. Each chip includes four independent DSP cores(532 DSP MIPS per quad core) and includes 640k words of internal program/data memory. The DM5441 thus provides 16 DSP cores, with a total of 2128 DSP Mips per module. Either base board, the 6U VME, V6M6 or V6M6 hot-swap, or the 6U CompactPCI C6M6 loaded with six modules peaks at 12768 DSP MIPS.

Host Port Interface

All data traffic between the local PCI bus of our VME or Compact PCI base board and a DSP passes through the host port interface (HPI) of that DSP. The HPI provides access from a PCI bus bridge to the DSP's internal memory.

The HPI bus on a DSP is normally a passive interface that responds to data transfers initiated elsewhere on the PCI bus. The DM5441 extends this capability to allow DSPs to request DMA transfers on the HPI bus between DSP internal memory and any PCI-accessible resource.

Shared SDRAM Memory

In addition to the 640k words of internal memory for each DSP chip, the DM5441 includes up to 8MB of shared SDRAM. This memory may be accessed from the local PCI bus or via DSP-requested DMA transfers between DSP internal RAM and SDRAM via the HPI bus.

DSP Synchronization

External interrupt signals 1 and 3 of all 4 DSPs are connected together. These signals allow all DSPs to synchronize to an external source, such as TDM superframe, TDM frame, or other interrupt source.

Module FPGA

The DM5441 module uses a Xilinx XC25200-5FG456C to interface the DSPs with the SDRAM and the baseboard's local PCI bus, I/O PCI bus and TDM buses.

JTAG Emulator Port

The DM5441 may be ordered with a JTAG emulator connector. This JTAG port connects to the 4 DSPs on each module in series to support debugging with an external emulator. When so equipped, the DM5441 may only be installed in module sites A or C of the V6M6 in order to gain access to the JTAG connector through the front panel.

TDM Interface

TDM serial data, such as data to/from H.110 or 100 BaseT interfaces, is accessed through the multi-channel buffered serial ports (McBSP) of the ‘5441s. The 16 DSPs share two common input and two common output McBSP buses. Timeslots on these buses are connected to timeslots on the VME (V6M6), Desktop PCI (DPT4), or Compact PCI(C6M6) TDM bus as directed by the TDM controller on the respective baseboard. Coordination of McBSP timeslot usage among the 16 DSPs on a DM5441 is distributed to those DSPs.

Specifications

Product Brochure
in PDF format.


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