DM6203

Our DM6203 smPCI module incorporates four TI 'C6203B DSPs to offer a peak rating of 8000 MIPS per module. With the advent of the TI 'C6203B, these DSPs now include 7 megabits of internal memory, which is sufficient to perform many telecom-related algorithms without the need for external memory. At 250MHz each DSP executes up to eight instructions per clock for a total of 2000 peak MIPS.

DM6203 smPCI Module

Processor

The number of the DM6203 modules allowed on a base board will depend on final power dissipation specifications for the C6203B. With present estimates, four of these DM6203 modules could be used, for our 6U VME V6M6 and V6M6HS base boards, yielding 32,000 MIPS peak. Our 6U compactPCI C6M6 base board will hold 6 modules for a total of 48,000 peak MIPS.

Global Memory

In addition to the 7 megabits of internal memory for each DSP, the module provides 32MB of synchronous DRAM on the Expansion Bus Interface shared by the four TI 'C6203B DSPs. This memory is accessed via DMA transfers initiated by the individual DSPs and is also accessible from the PCI bus.

Expansion Bus Interface

All data traffic between the PCI bus of our baseboard and a DSP passes through the Expansion Bus interface (EBI) of the DSP. The EBI supports direct memory access from the PCI bus to the entire memory space of the DSP. It also allows the DSP to initiate DMA transfers to/from the local PCI bus (as PCI master) or to/from EBI Global Memory. The four DSPs on a DM6203 share the same EBI.

DSP Synchronization

External interrupt signals 4 and 5 of all 4 DSPs are connected together. These signals allow all DSPs to synchronize to an external source, such as TDM superframe, TDM frame, or a time marker from another board on the SCSA bus.

Module FPGA

For it's standard configuration, the DM6203 module uses a Xilinx XC4028XLA to interface the DSPs with the local PCI and TDM buses. The module can optionally be populated with larger Xilinx devices up to an XC4085XLA to support application specific processing in the FPGA.

JTAG Emulator Port

The DM6203B may be ordered with a JTAG emulator connector. This JTAG port connects to the 4 DSPs in series to support debugging with an external emulator. When so equipped, the DM6203 may only be installed in module sites A or C of the 6U VME or 6U Compact PCI baseboard in order to gain access to the JTAG connector through the front panel.

TDM Interface

TDM serial data, such as data to/from the T1/E1 interfaces, is accessed through the three Multi-channel Buffered Serial Ports (McBSP) of the ‘C6203B. The McBSPs run at 8Mbit/s synchronously with the TDM buses, producing 128 8-bit timeslots in and 128 out per McBSP. On each timeslot, the baseboard selects which of the TDM buses are connected to each McBSP for input and which for output.

In normal operation on the 6U VME or 6U Compact PCI boards, two of the McBSPs can be used. In timeslot validity mode, one McBSP connects to TDM data and the other connects to the TDM validity buses. In non-validity mode both McBSPs can be used to connect to TDM data on all four TDM buses.

On our V6M6HS baseboards, additional TDM controls are available to support use of the third McBSP.

Product Brochure
in PDF format.

Back to top