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Desktop PCI Telephony (DPL3)
(Desktop PCI - QuicKit Telephony)
The DPL3 is a short-form PCI plug-in board for standard desktop
workstations. It provides either four L1 (E1/T1) bi-directional interfaces
or two L1 (E1/T1) bi-directional interfaces and one L3 (E3/DS3) bi-directional
interface. Connector types supported include RJ45, triax, and BNC.
QuicKit Telephony - PCI board DPL3
Line Interfaces
E1/T1 Line Interface
The DPL3 uses a PMC Sierra PM4354 Quad COMET for the E1/T1 interface.
The interface also includes over-voltage surge protection intended only
for use with intra-facility lines, and not for lines exposed to lightning
and/or power cross faults. It can either stream the four T1/E1 channels to the host
(with or without channelization)or process the data for each timeslot
in real-time. The default 120 ohm E1 configuration is software configurable
for 100 ohm T1 applications. The 75 Ohm impedance option for E1 is specified with
an 'A' suffix to the part number.
E1/T1 Frame Formats
The DPL3 supports all standard E1 and T1 framing formats.The DPL3 is available
with several endplate jacks: RJ45, BNC or triax.
E3/DS3 Line Interface
The DPL3 uses an Exar E3/DS3 chipset for the E3/DS3 interface.
The interface also includes over-voltage surge protection intended
only for use with intra-facility lines, and not for lines exposed to
lightning and/or power cross faults. It supports 75ohm coaxial connections
over cable lengths up to 1100 feet.
Currently planned Frame Formats
The DPL3 includes framers that handle G.751 and G.832 E3 frame formats.
Each of these framer formats has multiple options for payload handling.
- G.751 Raw Payload.
- All bits from the E3 signal other than framing and fixed function bits
are collected from or delivered to the host computer without interpretation.
- G.751 E1 Payload.
- The payload is interpreted by an E3-to-E1 multiplexer / demultiplexer to
produce 16 independent E1 streams. Each E1 stream is provided with a separate
E1 framer (16 framers total). The E1 streams are handled in a variety of formats
as described in the DPL3 specifications.
- G.832 Raw Payload.
- All bits from the E3 signal other than framing and fixed function bits are
collected from or delivered to the host computer without interpretation
using G.832 framing.
- Unframed E3.
- Raw 34.368 Mbps bit stream is deposited into host memory with arbitrary alignment
and without interpretation. Output data is taken from host memory and written to
the E3 output without formatting (other than the low-level HDB3).
Future additions to Frame Formats
- G.751 HDLC Payload. *
- The raw payload is interpreted as a single high-speed HDLC stream, with the HDLC
packets collected from or delivered to the host computer.
- G.832 HDLC Payload. *
- The raw payload is interpreted as a single high-speed HDLC stream, with the HDLC
packets collected from or delivered to the host computer using G.832 framing.
- G.832 ATM Payload. *
- G.832 payload is interpreted as 53-byte ATM cells. The cells are deposited into
or retrieved from host memory without interpretation, other than discarding idle cells.
No AAL adaptation layer processing is performed by the DPL3.
Channelization
The DPL3 FPGA performs the functions necessary for channelization (multiplexing and
de-multiplexing) of E1/T1 and/or E3/DS3 streams. A 16 MB SDRAM is used to store channel
descriptors (downloaded from the host) and raw data.
The FPGA interface includes the host PCI interface, including a DMA controller that
manages transfer of channelized data between host workstation memory and DPL3 memory.
Software
CAC provides a host workstation software API to support development of user applications.
Host operating systems supported include Solaris and Linux.
Available modes include:
- Full channelization.
Each E1/T1 timeslot is opened, read and/or written as a distinct stream.
- Arbitrary bonding.
Multiple timeslots can be combined in
arbitrary ways to create higher-speed streams.
- Unchannelized.
Each E1/T1 line is accessed as a single stream.
For T1, the framing bit is not part of the stream.
For E1, timeslot 0 can be part of the stream or not, as desired.
Also for E1, an unsynchronized mode is available in which no E1
framing is present in the E1 signal.
Specifications
Part Number |
Endplate Connectors |
| PC3100 |
Quad-L1(No connectors) |
| PC3100A |
Quad-L1(No connectors),
75 Ohm |
| PC3110 |
Quad-L1(BNC) |
| PC3120 |
Quad-L1(triax) |
| PC3130 |
Quad-L1(RJ45) |
| PC3300 |
Dual-L1(No connector),
Single-L3 (No connector) |
| PC3300A |
Dual-L1(No connector),
Single-L3 (No connector),
75 Ohm |
| PC3311 |
Dual-L1(BNC),
Single-L3(BNC) |
| PC3312 |
Dual-L1(BNC),
Single-L3(triax) |
| PC3321 |
Dual-L1(triax),
Single-L3(BNC) |
| PC3322 |
Dual-L1(triax),
Single-L3(triax) |
| PC3331 |
Dual-L1(RJ45),
Single-L3(BNC) |
| PC3332 |
Dual-L1(RJ45),
Single-L3(triax) |
| SDRAM (MB) |
16 |
| PCI board style |
Short |
| PCI bus width |
32 bit |
| PCI bus speed |
33/66 MHz |
| PCI voltage |
Universal |
| MTBF (kHr) |
XXXXXX |
| +3.3v power (A) |
<1.5 Amps
|
| Size (inches) |
6.6 x 4.2 |
Please tell us about your
configuration requirements.
We would be happy to contact you.
Product Brochure
in PDF format.
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