IM4SER smPCI Modules
The IM4SER provides DMA supported serial communication for either the VME (V6M6)
or Compact PCI (C6M6)
baseboard carrier boards. The serial interface consists of four
independent serial channels. Each channel provides HDLC/ASYNC support
and a variety of serial interface configurations. Serial communication
control is provided by the Seimens PEB 20534.
The primary components are the :
- Linear Technology Multiprotocol Transceivers (four),
- Siemens DMA Serial Communication Controller, and
- Xilinx Spartan FPGA.
The IM4SER module is connected to the outside world using a single
VHDCI connector. Four complete serial channels go through the VHDCI connector.
Control and data signals are routed to the Siemens chip while clocks
are routed to the FPGA. The Siemens chip PEB 20534 is capable of
simultaneous control of numerous serial interfaces and is the heart of this module.
Local PCI Bus provides control
Access to the PEB 20534 control, status and data registers is provided
through the PCI interface. A local bus interface provides access to the FPGA.
All transactions to the host go through the PCI interface. The xilinx
provides clocks for each serial channel and controls some baseboard signals.
The IM4SER uses the FPGA configuration data stored in the Flash ROM on the
VME or Compact PCI baseboard. The configuration space base addresses are
determined by physical hardware connections.
I/O space base addresses are determined by convention and are hard coded into
various software modules.
IM4SER Module Block Diagram
Incoming and outgoing serial data is accessed by other PCI modules via DMA;
provided by the PEB 20534.
The PEB 20534 provides FIFO storage between host memory and both incoming
serial data and outgoing data.
The primary method for transferring incoming and outgoing E1 data is via the TDM
subsystem. The serial data input and output of the E1 framers are connected to the
TDM data busses through elastic storage buffers, allowing the TDM clock rate to be a
multiple of the E1 data rate.
Data is transferred between a TDM data bus and an elastic storage buffer on a
slot-by-slot basis based on commands stored in the TDM subsystem MAP RAM.
CAC provides firmware programming that aids in efficient and accurate use of
E1 elastic buffers. The methods implemented include:
- Efficient read/write enhancements
- User configurable framing parameters
- Protection against data loss
- Dynamic redefinition of the TDM clock, and
- Automatic filtering of repeated data
Efficient read/write enhancements
Exactly 32 bytes (time slots) per TDM frame must be transferred to and from
each of the E1 line's elastic buffers. It is possible to read and write the buffers
for both lines during the same time slot. It is also possible to unload a byte from
an incoming buffer without driving the data onto a TDM bus. This allows unused data
to be purged without using up TDM bandwidth.
User configurable TDM framing parameters
TDM frames must always be set for 125 microseconds. They may be configured as 32
slots at 2.048 MHz, 64 slots at 4.096 MHz or 128 slots at 8.192 MHz.
When frames of 64 or 128 slots are used, we recommended
that the E1 slots be spread evenly across the available TDM time slots.
The E1 data frames, incoming and outgoing, are aligned with the TDM frames.
Outgoing multiframes are synchronized with the multiframe sync generated by the
TDM subsystem. Incoming multiframes are synchronized with the receive multiframe
sync for each line.The first incoming slot contains framer status information
while the other 31 E1
data slots are available as received from the RSER pin of the framers.
Protection against data loss
Most applications have the TDM subsystem clock derived from the
clock received from an incoming E1 line. The E1 transmit clock is then
usually derived from the TDM subsystem clock.
In a few situations, the timing of multiple incoming E1 lines may be
derived from different
time bases; their clocks may be running at slightly different frequencies.
Depending on which receive clock is faster, data from one of the incoming
lines could be either lost or repeated as the elastic storage buffer
in the framer chip under-flows or over-flows. This data loss or repetition
occurs at a frame boundary; an entire
frame is either lost or repeated at a time.
Dynamic redefinition of the TDM clock
The IM4SER has logic to compare the frequencies of its two receive clocks, to
determine which is faster and to use the faster of the two clocks to derive
the TDM subsystem clock. Host applications may
select this mode of operation. With TDMCLK derived from the faster E1 receive
clock, any frame slips occurring on the other E1 line will be due to elastic store
under-flows and data will be repeated rather than lost. Should the frequencies of
the two incoming E1 lines drift, the IM4SER will automatically switch which receive
clock is used to derive TDMCLK. Furthermore, if one of the framers is not in sync,
the IM4SER will automatically select the other framer's receive clock to derive the
To insure that data is not lost in the case where the two incoming clock rates are
very close and wavering, the derived TDM clock is adjusted to be approximately 3.8
PPM more than the faster received rate, which will cause repeated frames from both
framers. This mode is "on"
by default but may be overridden.
Automatic filtering of repeated data
Additional logic provides a mode by which
TDM data from a slipped frame is invalidated. Modules
capable of interpreting the TDM Valid signals filter out data
repeated due to slips.