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IMATM155

The IMATM155 module provides an interface between an ATM OC-3 optical link and the PCI bus of a V6M6 VME board. It includes an optical transceiver, a PHY chip, a SAR chip and associated timing components. It supports hardware-level filtering of ATM cells based on Virtual Circuit and performs autonomous AAL3/4 and AAL5 processing. AAL1 and AAL2 require assistance from a processor attached to the PCI bus, such as a PM4700 module with an R4700 Orion MIPS processor.

Optical Transceiver

The IMATM155's transceiver is made of an HP optical transmitter and receiver, both of which protrude through the front panel of the V6M6. They accommodate SC-type fiber optic connectors and are intended for use with 1300nm multimode fiber running at 155Mbps.

PHY and Timing Components

An IDT77155 chip provides PHY functions including optical transceiver interface, clock recovery, SONET and ATM framing, and UTOPIA interface. Timing components on the module provide the ability to do one of the following:

  • lock the V6M6 TDM clocking to the 8KHz SONET framing
  • generate the optical clocking based on the TDM 8KHz framing
  • allow the optical and TDM timing to operate independently

SAR

An IDT77211 NICStAR chip provides ATM cell processinq functions. It transmits and receives ATM cells with the PHY via a UTOPIA interface and interfaces to the V6M6 via its PCI interface. SRAM attached to the SAR provides:

  • the ability to filter and direct ATM cells based on the Virtual Circuit identified in each cell
  • plentiful buffering for cells in transit
  • a transmitter schedule table for managing output cell streams
  • buffering for AAL3/4 and AAL5 packets during segmentation and reassembly
The IMATM155 has bus-mastering capabilities that gives the SAR direct access to PCI memory to deposit and retrieve cells and packets of data. This minimizes the load on the associated processor and allows long bursts of traffic at full OC-3 rate.

The SAR handles all required details of segmentation and reassembly for AAL3/4 and AAL5 packets. Other types of traffic (e.g. AAL1 and AAL2) are treated as raw cells by the SAR and are placed or taken from queues in PCI memory.

Required Support Processor and Operating Environment

The IMATM155 requires another processor on the PCI bus, such as the PM4700A, to initialize the PHY and SAR, manage the flow of ATM traffic and handle exception conditions.

CAC supplies a real-time Unix-like kernel for the PM4700A with support for the IMATM155. In addition, CAC has implemented AAL2 to comply with the protocol specification I.363.2.

Note that the kernel requires support from a CAC-supplied server process in the VME host computer. This server is currently supported on SunOS, Solaris and VxWorks for the PowerPC.


Specifications

Product name

IMATM155

Physical Interface

OC-1, OC-3, STM-1, 1300nm multimode SC

P/N code

MPA1

MTBF (kHr)

618

+5v power (A)

0.8 Amps

Max per V6M6

2

V6M6 sites

A or C

Size (inches)

2.9 x 2.75


 

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