PM7000
Featuring the highest performance embedded MIPS processor available
today, the PM7000 module includes a QED
(PMC-Sierra) RM7000A 64-bit floating-point microprocessor and 64MB of
SDRAM. This RISC processor initializes the PHY and SAR of the IMATM, manages the
flow of ATM traffic and handles exception conditions on our
V6M6 or
V6M6 Hot-swap base boards
and our 6U Compact PCI
C6M6 base board.

PM7000 smPCI Module
The RM7000A processor can execute two instructions
per clock, so the currently available 350MHz devices yield a peak
instruction rate of 700 MIPS. It includes 16KB
primary instruction and data caches, plus a 256KB internal secondary cache.
The RM7000A processor is a 64-bit floating-point microprocessor.
The chip features:
- pipelined floating-point ALU
- separate integer and floating-point ALUs eliminates dependent latencies
- floating-point multiply-add/subtract instructions
- low-latency multiply-add and conditional move instructions
- single cycle repeat instruction
- two-way set associative cache increases hit rate
Details on the RM7000A can be found on PMC-Sierra web site www.pmc-sierra.com
Error Detection Capability
In addition to the 64MB of on-board local DRAM,the 64MB
of local SDRAM includes a robust error detection capability. It is capable
of detecting all single- and double-bit errors in a 32-byte cache line.
When enabled, this error detection mode consumes 4MB of the 64MB, leaving 60MB for user
applications.
PCI bus Master
The module is a PCI bus master and target. This makes
the module’s memory available to other PCI
masters, as well as enabling the RM7000A processor to reach any PCI-accessible
memory on the baseboard or on other modules.
The PCI master logic includes a DMA controller to support memory-to-memory
copies with low CPU overhead. The module
comes with a connector to the processor's RS232 port for debugging purposes.
In addition to the 64MB of on-board local SDRAM, the PM7000 module
provides a PCI bus master enabling it to access
the carrier board's global memory as well as other modules.
Inter-module isochronous communications are accomplished
via the four TDM buses.
Specifications
| Product name |
PM7000
|
| Processors |
PMC-SIERRA RM7000A
|
| P/N code |
MCCB
|
| RS232 ports |
1 (Optional)
|
| Clock (MHz) |
Up to 400
|
| Code cache (kB) |
16
|
| Data cache (kB) |
16
|
| DRAM (MB) |
Up to 256
|
| MTBF (kHr) |
N/A
|
| +5v power (A) |
1.2
|
| Max per V6M6 |
4
|
| V6M6 sites * |
Any
|
| Max per C6M6 |
4
|
| C6M6 sites * |
Any
|
| Size (inch) |
2.9 x
2.75
|
| * without serial port connector |
Product Brochure in PDF format.
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