Desktop PCI Telephony (DPT)

(Desktop PCI - QuicKit Telephony)

DPT4 stands for Desktop PCI Telephony, 4-spans. This short PCI bus plug-in board provides four T1/E1 interfaces for desktop workstations. It can either stream the four T1/E1 channels to the host (with or without channelization) or process the data for each timeslot in real-time. Either 12 or 24 TI 'C5420 DSP's can be added for compute-intensive telephony applications. These optional DM5420 smPCI modules feature 12 dual-core fixed point DSP's. An H.110 bus enables two or more DPT4 boards to transfer data among themselves or with other PCI boards.

DPT4 Desktop PCI baseboard

Line Interfaces
The DPT4 uses 4 combined E1/T1 line interface/framer chips from PMC-Sierra, the PM4351 COMET. This highly configurable device supports all current E1 and T1 standards and can operate both in long-haul and short-haul applications.

The DPT4 may be ordered with either 75 or 120 ohm impedance for E1. The 120 ohm E1 configuration is software configurable for 100 ohm T1 applications. It includes over-voltage surge protection intended only for use with intra-facility T1/E1 lines, and not for lines that are exposed to lightning and/or power cross faults.

The DPT4 is available with several endplate jacks: RJ45, BNC or triax. The triax jacks are used with shielded twinax cables terminated with Trompeter PL75 (or equivalent) connectors.

With BNC or triax connectors, the four on-board jacks may be configured by shunts to support four receive-only or four transmit-only E1/T1 circuits or two bidirectional circuits. To support four bidirectional circuits, the DPT4 includes four 2-pin headers that may be used to connect to four additional jacks mounted on an adjacent PCI bracket or elsewhere on the chassis.

Local Processor
The DPT4 includes a 100MHz MIPS processor subsystem based on the RC32364 chip from IDT. The subsystem includes 16MB of global SDRAM, 2MB of flash memory, interfaces to the 4 COMET chips and a PCI interface. The purpose of the MIPS processor is to manage the COMET chips and to assist with any required channelization (multiplexing and demultiplexing) of the E1/T1 streams.

The workstation processor generally communicates with the MIPS processor rather than directly with the E1/T1 framers. The MIPS PCI interface includes a DMA controller that is responsible for transferring E1/T1 data between workstation memory and MIPS memory.

Software
CAC provides MIPS and workstation processor executables to support user access to the E1/T1 lines. Available styles include:

• Full channelization. Each E1/T1 timeslot is opened, read and/or written as a distinct stream.
• Arbitrary bonding. Multiple timeslots can be combined in arbitrary ways to create higher-speed streams.
• Unchannelized. Each E1/T1 line is accessed as a single stream. For T1, the framing bit is not part of the stream. For E1, timeslot 0 can be part of the stream or not, as desired. Also for E1, an unsynchronized mode is available in which no E1 framing is present in the E1 signal.
• HDLC processing. Limited handling for HDLC channels by the COMET chips and the MIPS processor will provide for typical D channel usage for ISDN PRI signals.

DPT4 supports host operating systems for Windows (2000, 2003 & XP), Solaris (versions 2.6 - 2.9 and 2.10 on Sparc only) and Linux (kernel 2.4 & 2.6).

Specifications

Product Brochure
in PDF format.

Back to top