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Moving telecom and audio data from one source to one or more
destinations is most efficiently accomplished through a serial bus. Most EmPack
resources, such as the T1/E1 interface chips and DSPs, have built-in serial interfaces for
this purpose. Serial 8-bit data units (typically, but not necessarily, mlaw or A-law
compressed audio samples) are routed among these resources as a timeslot in one of the EmPack’s
TDM (Time-Division Multiplexed) buses. Each TDM bus can carry 128 timeslots in a manner
similar to the T1’s TDM with 24 timeslots or the E1’s 32 timeslots. The routing
of each timeslot (source and destinations) is setup by user software running on the host
computer. The EmPack’s firmware interprets these commands to manage the
routing of data, making the whole process invisible to each resource. The sourcing device
simply outputs the data through it’s serial port and the EmPack places it in
the desired timeslot of the correct bus. Likewise, the serial port of the receiving
device(s) sees only data from the timeslots determined by the host’s software. A
resource that receives multiple timeslots can be interrupted by the superframe to keep the
incoming data in order.
TDM Bus Timing
All TDM buses run synchronously, each with the same bit clock, timeslot definition, frame
duration and frame sync pulse. The TDM bus runs at 8.192MHz, with 128 8-bit slots per
frame. The frame sync occurs every 128 slots (8 KHz). The multiframe sync lasts for one
entire frame (125 ms) and is programmable to occur either never or once per 2 to 32
frames.
TDM Conditional Transfers
Each TDM bus has a "data valid" signal associated with each timeslot.
Connections established through the TDM system provide the opportunity to transmit a data
item from source to destination(s) each time its assigned slot occurs. If the source has
no data to transmit at this time, "data valid" is not asserted, preventing the
destination(s) from reading invalid data. This feature is used to accommodate
"slips" which result from slightly different clock rates between multiple T1/E1
sources.
TDM Continuation Slots
When 16 or 32-bit data is sent over the TDM bus, two or four consecutive
timeslots are used. Defining the second, third and fourth timeslots as "continuation
slots" makes this link appear to the source and destination resources as a single 16
or 32-bit timeslot.
TDM Bus on the Foundation Board
The EmPack foundation board has the ability to map timeslots from both the on-board
T1/E1 interfaces and the external SCSA bus onto its internal TDM bus. To route T1/E1 data
to the mezzanine boards, the incoming data from both interfaces must go through one of the
six TDM buses. Likewise, all outgoing T1/E1 data is restricted to one TDM bus. Since each
bus consists of 128 timeslots, only one is required to handle all bi-directional traffic
for both telecom interfaces. Similarily, up to 128 timeslots from the external SCSA bus
can source one internal TDM bus and only 128 SCSA timeslots can be the destination of one
TDM bus.
TDM Bus on the Mezzanine Connector
The EmPack’s mezzanine connector carries 6 TDM buses for a total of 768
timeslots, any combination of input or output. These buses are made available to the
serial ports of the processor(s) on the mezzanine boards.
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