DM549 small mezzanine PCI (smPCI) Module
In addition to the 32K words of internal memory for each DSP, two
of the 12 DSPs have 256KW of one wait-state external SRAM which can be
used as program memory.
Host Port Interface
All data traffic between the PCI bus of our baseboard and the DSP
passes through the host port interface (HPI) of the DSP. The HPI
supports direct memory access from the PCI bus to a 2kW region of the
DSP's internal memory. Data transfers within this 2kW HPI region simply
involves the host library functions and does not require any DSP cooperation.
To support indirect access to the rest of the DSP's internal memory, CAC
supplies DSP code to be linked with the user's application. The host
creates a descriptor which specifies a block of memory to be transferred
and then interrupts the DSP.
To transfer large data buffers with the host, a DSP can request to
DMA a block of HPI memory to/from the baseboard's PCI global memory. The
host can then efficiently transfer data to/from PCI memory without
interfering with the DSP.
High speed transfers to/from the HPI can also be initiated by PCI
masters that are capable of PCI burst transfers.
For example, a PM4700A MIPS processor module generates 32-byte PCI
bursts when reading or writing cache lines to/from targets on the
PCI bus. Each HPI bus has a target burst buffer and can empty or
fill 32 bytes in approximately 2 uS.
Inter-DSP Serial Bus
The 12 DSPs are divided into two groups of six on two inter-DSP
serial buses which are intended for low bandwidth traffic (e.g. control
messages). See the TI C54x user's manual for details on the use of
this serial port.
External interrupt signals 1 and 3 of all 12 DSPs are connected
together. These signals allow all DSPs to synchronize to an external
source, such as TDM superframe, TDM frame, or a time marker from another
board on the SCSA bus.
The DM12C549 module uses a Xilinx XC4028XL to interface the DSPs
with the local PCI and TDM buses. The module can optionally be
populated with larger Xilinx devices up to an XC4062XL to support
application specific processing in the FPGA.
JTAG Emulator Port
The DM549 may be ordered with a JTAG emulator connector. This
JTAG port connects to the 12 DSPs in series to support debugging with
an external emulator. When so equipped, the DM549 may only be
installed in module sites A or C of the V6M6 or C6M6 boards in order to gain access
to the JTAG connector through the front panel.
TDM serial data, such as data to/from the T1/E1 interfaces, is
accessed through the buffered serial ports (BSPs) of the 'C549s via DMA
to a reserved 256-word block of DSP internal memory. The BSPs run at a
fixed 8 MHz bit rate, synchronous with the TDM buses, producing 128
8-bit timeslots in and 128 out per BSP. On each timeslot, the
baseboard selects which of the TDM buses are connected to BSP for input
and which for output.
For TDM input, each DSP receives all 128 timeslots. An interrupt
is generated after each TDM frame and the DSP's interrupt service
routine retrieves the timeslots it wants from the frame buffer.
For TDM output, each DSP is responsible for placing its data into
the proper timeslot locations in BSP memory. The DSP will be interrupted
for each TDM frame and must deposit its new output data before the next
TDM frame interrupt. Sample code for TDM input and output is supplied
For applications not requiring timeslot validity, a second BSP can
process an additional 128 timeslots of data for a total of 256 input
and 256 output timeslots. These timeslots may be allocated as desired
between the 12 DSPs on the module.
|Internal SRAM (kW)*
|External SRAM (kW)**
|+5v power (A)
|Max per V6M6
|V6M6 sites ***
|C6M6 sites ***
2.9 x 2.75
* per processor
** for 2 of the 12 processors
*** without JTAG connector