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Efficiency in routing data among the multiple processors and
mezzanines for the VME6U6, VME9U12, V6M6, V6M6HS and EmPack is
accomplished by a Time-Division Multiplexed (TDM) bus
subsystem. The TDM bus is optimized to carry isochronous
communications. Isochronous refers to traffic which must
be carried at a steady rate (such as digitized audio) as
opposed to traffic carried in bursts, which is typically
carried in packet structures or on parallel buses.
TDM Bus Timing
All four serial buses of the TDM run synchronously, each
with the same bit clock, time slot definition, frame
duration and frame synch pulse. The TDM bit clock rate is
set by a baseboard or mezzanine board oscillator.
For VME6U6 and VME9U12 boards the default clock rate is
16.384 MHz if no mezzanine boards are used,
Restrictions may be imposed by the specific
mezzanine board(s) used and by the number of boards
connected via the TDM expansion port.
For the V6M6 board,
the TDM bus normally runs at a 8.192MHz rate. If
populated with only PM4700, MM32 or IM10BT
modules (no IMSCSA), its rate can be 16.384MHz.
T1 and E1 Timing Considerations
For normal T1 applications the bit rate is 1.544 MHz
providing 6.176 Mbits/sec of bandwidth on the four TDM
buses (4 x 1.544). However, an on-board phase locked loop
allows TDM rates of 2.048 and 6.144 MHz. This method
increases the number of time slots for higher throughput
while still conforming to T1 timing. The E1 rate is
normally 2.048 but speeds of 4.096 and 8.192 are
available.
TDM Ram
Operation of the TDM bus is directed by the contents of a
dual-port memory which is loaded via the VME bus. Tandem
memory banks are used to make changes in a consistent
manner. One memory bank actively controls the TDM bus
while the other is modified by the host. The TDM ram
controller issues a "switch bank" command to
activate the changes.
Superframe/Frame/Time slot
A device is connected to the bus when it is given a
specific time slot on one of the four buses. This slot is
programmed to be 8, 16, or 32-bits wide. A programmable
number of time slots (up to 128) make up a frame and up
to 32 frames make a superframe.
The connection pattern, as programmed in the TDM ram,
is repeated for each frame. A synch pulse that separates
consecutive superframes is tied to the SY signal of each
DSP, which can either be detected by the DSP or can be
used to generate an interrupt. This is important for
applications that send or receive more than one time slot
of data per frame in any given DSP since the DSP needs to
know which time slot is associated with each inbound or
outbound data item.
On a given TDM bus, each time slot can have only one
source but can have more than one destination. For
example, the same data from a T1 slot can be directed to
both a CODEC and several DSPs, simultaneously.
Point-to-point, or point-to-multipoint connections
appear as dedicated links between the resources
participating in the connection. The user's application
program controls the configuration map through a library
of C-callable functions.
Conditional Transfers
Each TDM bus has a "data valid" signal
associated with each time slot. Connections established
through the TDM system provide the opportunity to
transmit a data item from source to destination(s) each
time its assigned slot occurs. If the source has no data
to transmit at this time, "data valid" is not
asserted, preventing the destination(s) from reading
invalid data.
Continuation Slots
Many times DSP-to-DSP communications involves 32-bit
data, such as floating point numbers. However, T1 and
CODEC data on the TDM bus must be 8-bit data. To
accommodate both formats, the TDM map may be programmed
for two or four consecutive time slots (one normal and
one or three continuation slots). It appears to the DSPs
involved in this link as a single 16 or 32-bit time slot.
Multiple VME Boards
When linking several dsp boards via the tdm expansion
bus, one board must serve as the master for the clock,
time slot definition and framing while the other boards
are slaves. A library of functions is provided as a means
to initialize the T1 boards in a master, slave, or
independent mode.
The 6UT1 and 6UE1 boards have a buffered TDM expansion
port that is separate from the VME6U6 baseboard's J4 TDM
port. A group of boards linked via their J4 ports can be
linked with another group by tying the expansion port of
one board (6UT1, 6U4T1, 6UE1, 6U4E1 or 6UEXP) from each
group.
The TDM expansion port links the TDM subsystems of
multiple boards by flat ribbon cable. One board is
designated as the master and the rest are slaves to the
same TDM clock, time slot definition and framing.
*VME6U6 only
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