Solid-state Delay Line

The V6SSDL baseboard boasts up to 8GB of delay memory, with an optional 8GB mezzanine available. The single-slot VME unit provides three configurable FPDP connectors. Depending on the memory size, data sample size, and input clock rate, the available delay may be as much as 100 seconds for MHz-range sampling, or hundreds of hours for audio-rate sampling.

Tapped Delay Line Function

One of the ports of the V6SSDL is configured with jumpers as the input, with the other ports providing outputs with independently programmable delays. With both outputs enabled, it becomes a tapped delay line. Either output can be restarted at any time with any data in the delay line.

FPDP Characteristics

The three FPDP interfaces are configurable for 32-bit sample data or for 16-bit packed (low/high) or unpacked (low or high) samples. Support is available for 10-bit samples, packed three to a 32-bit transfer. The ports have selectable termination, supporting both FPFP/R and FPDP/RM input functions.

The ports operate at clock rates up to 20 MHz with the FPDP TTL clock, or up to 40 MHz with the PECL clock. Skew between the input and output clocks is less than 2.0 ns; it varies less than 1.0 ns over all boards and all rated temperature and voltage ranges.

Treatment of the FPDP suspend signal depends on the V6SSDL configuration. For fixed delays, it can ignore the signal or propagate it upstream. In flexible FIFO mode, the V6SSDL can absorb bursty data to its capacity and output it at a rate limited by the suspend signal from the downstream board

VME characteristics

The V6SSDL VME slave mode interface supports both A16/D32 and A32/D32 access, including block transfers (BLT). VME accesses initialize the board, configure the delay line (e.g. set the desired delay), control its operation (start/stop), monitor the state of the board, examine data, and control self-test diagnostics.

VME Snapshots

The host may also download recorded or pre-computed data to be sent out one or both output ports.

Xilinx Virtex FPGA
The overall operation of the V6SSDL is controlled by a large field-programmable gate array (FPGA) manufactured by Xilinx. Onboard flash memory supports several alternative FPGA configurations. Standard V6SSDLs use a Virtex XCV300 device, which provides 300,000 gates. The V6SSDL may be specially ordered with larger Virtex chips, up to the XCV800 with 800,000 gates. This larger capacity could support special user-specified signal processing algorithms to analyze or transform the FPDP data streams.

Delay Memory
The delay memory on the standard V6SSDL is implemented with 128 Mbit SDRAM chips. The baseboard includes 128 of these chips in its main memory array, plus two additional SDRAMs for special purposes. The main memory array operates at clock rates up to 75 MHz, and its access width is 64 bits. The maximum memory bandwidth is 600 MB/s. On the standard configuration, an optional SDRAM mezzanine board extends the V6SSDL delay memory to 4 GB in a single VME slot. The delay available depends on the memory size, sample width, and FPDP clock rate; some typical cases:

Error Detection & Correction

In addition to chip failures, large arrays of memory are subject to occasional single-bit errors induced by cosmic radiation or radioactive impurities in the chip packaging material. The V6SSDL includes error detection and correction capabilities designed to deal with these random events.

Each block of 128 FPDP samples in the V6SSDL delay memory is protected with a 16-bit ECC code. This ECC is capable of correcting any single bit error and detecting any double bit error within the block. The ECC data is stored in the second special SDRAM on the V6SSDL. If the ECC detects a single bit error when a data block is retrieved, the data block is corrected before it is delivered to an FPDP output. Thus, the delay line is not subject to random single-bit errors. Host monitoring of errors can identify a marginal or failing chip to be replaced by the spare.

Data Preservation
The V6SSDL allows the host to preserve the data in a dynamically defined region in delay memory as long as it is needed. Without interrupting the data streams into and out of the delay line, the preserved region can be dumped to the host or sent out an output port after it would otherwise have been overwritten.