220
MFLOPS
The VME6U6 maximizes processing power on a 6U card by
utilizing six independent Lucent general purpose DSP32C
chips, each with its own private memory, for a maximum
throughput of 220 MFLOPS or 110 MIPS. A 50 MHz version,
VME6U6/50, is rated at 150 MFLOPS and 75 MIPS. A
user-configurable serial bus (TDM) provides
inter-processor communications. Add-on mezzanine boards
provide optional interfaces to external signals and
telephony communications.
The standard Lucent development tools include a
C-compiler, assembler, and run-time library of matrix,
trig, and signal processing functions (DSP32C & DSP3210
Software/Lucent
Applications Library). The CAC support library adds
C-callable functions and a UNIX device driver to control
the VME6U6 board. Several demo and diagnostic utilities
are supplied as examples to quick start your development.
D3BUG, our C-source debugger, facilitates development of
your DSP application software.
Vectored Interrupts
By writing to its PIR register, each DSP can
generate a vectored VME interrupt. Control is provided by
an interrupt mask and status register. The DSPs can be
interrupted by the host by asserting either of the
interrupt pins INTREQ1 or 2. These signals are cleared by
the DSP acknowledgement IACK1 or 2.
Back to Diagram
VME Bus Interface
Both slave (programmed I/O) and master (DMA)
modes can be used to transfer data between the host's and
DSP's memory - 32 bits in a single VME bus access. Slave
mode is used to communicate with non-DSP resources or to
access the DSP's memory as 8, 16, or 32-bit data. A
BROADCAST mode supports simultaneous, write-only
transfers to all DSP chips on a single board.
Back to Diagram
Base Address
Four hex rotary switches set the memory address
(A24 standard or A32 extended). Each board occupies 128K
bytes of address space.
Back to Diagram
4 TDM Serial Buses
The time-division
multiplexed (TDM) subsystem provides communication
links between DSPs on the baseboard, across multiple
boards, and to the mezzanine subsystems mounted on each
board. FPGA chips control the four buses which are all
clocked at the same rate.
Any DSP or mezzanine board can drive or receive from
any subset of the four TDM
buses. Data flow between DSPs, other boards, and
mezzanine devices is configured by a user's program on
the host.
Back to Diagram
TDM Expansion
The TDM subsystems of up to 12 VME6U6 boards can
be inter-connected to enable communications between the
resources of all boards. The number of boards that can be
linked depends on the TDM clock rate. The TDM bus can
also be used to communicate with a user's custom board in
another VME slot. The TDM expansion connector is an
integral part of the baseboard and does not require a
mezzanine board.
Back to Diagram
VME Backplane Connectors
Only standard VME signals and power pins are
used. None of the A or C rows of P2 are used.
Back to Diagram
Six Lucent DSP32Cs
Each processor communicates with the host via its
parallel port and with other resources on the board via
its serial port and TDM subsystem. Each DSP is clocked at
an 74 MHz rate yielding 37 MFLOPS and 18 MIPS per DSP.
Back to Diagram
DSP FPGA
Each of 3 field programmable gate arrays controls
a pair of DSP chips, providing VME address decode, read
and write transfers between the host and each DSP chip,
external interrupt control, TDM interface to the DSPs'
serial ports, and control of the status LEDs.
Back to Diagram
DSP Memory
Each DSP has 6k bytes of internal RAM and 512k
bytes of private zero wait-state external static RAM.
This memory is directly accessible by the DSP's program
or by the host via the DSP's parallel port DMA transfers.
Back to Diagram
Mezzanine Board
Connector
Optional add-on boards provide analog I/O,
telephony interfaces (T1, CEPT-E1), auxiliary DSP
processors, and custom interfaces. The VME6U6 may host a
single mezzanine board and still occupy a single slot.
See bottom of page for available
add-on boards.
Back to Diagram
VME Enable/Disable
Switch
Switch controls the board's ability to respond to
or generate activity on the VME bus. This can be used to
isolate the board while performing system diagnostics.
Back to Diagram
Reset
Momentary push button provides a hardware reset,
canceling any VME transaction in process and
reconfiguring the programmable gate arrays from an
on-board EPROM.
Back to Diagram
Status LEDs
Two rows of LEDs indicate VME activity and
programmable status of each DSP. The SLAVE LED lights
during programmed I/O and MASTER lights during each DMA
cycle. Each of the remaining pairs of LEDs are controlled
by either the DSP or host writing to a reserved memory
location.
Back to Diagram
VME6U0/0K
P/N: 6V1A
If your application requires more mezzanine boards but
not more DSPs, a low cost version of the 6U board is
available without processors or memory. The board has a
fully functional TDM subsystem that can be linked with
the TDM of other DSP boards so that the resources of its
mezzanine board are accessible as if it were a fully
populated board.
6UEXP
P/N: 6MX1
Clusters of VME6U6 boards sharing their own TDM bus
can be linked by the 6UEXP mezzanine board. Each cluster
is controlled by its own TDM map as it routes data among
its DSPs and their resources. The 6UEXP bridges these
local TDM buses on a time-slot basis.
Specifications
| P/N code |
6V1A
|
6V1B
|
6V1C
|
| Clock |
0
|
50MHz
|
74MHz
|
6 Lucent DSP32C-F35 processors
6U size VME board
Bus master 32-bit DMA transfer
32-bit DMA address ptr, 14-bit word count
Slave memory mapped I/O
32/24 bit addressing (MA32,SA32/24)
32/16 bit data transfer (MD32,SD32/16)
74/50 MHz operation
512k byte private SRAM per DSP |
| Size |
6U 160mm
|
| MTBF |
123,000
hours @ 40°C
|
| Power |
3A @ 5V
|
Data Transfer Rates:*
DSP to
VME via |
|
DMA:
Programmed
I/O: |
2.3 MB/sec
2.9 MB/sec
|
| VME to DSP via |
|
DMA:
Programmed
I/O: |
2.0 MB/sec
5.8 MB/sec
|
| *(These rates are measured by an
application program running on a Force 20. Actual
speed depends on host computer and size of data
buffer being transferred.) |
|
