440 MFLOPS
The VME9U12 uses twelve independent Lucent general
purpose DSP32C processors, each with its own private
memory, to obtain a maximum throughput of 440 MFLOPS or
220 MIPS. A 50 MHz version, VME9U12/50, is rated at 300
MFLOPS and 150 MIPS. A user-configurable serial bus (TDM) controls
inter-processor communications. Room for two add-on
mezzanine boards provide optional interfaces to external
signals and telephony communications.
The standard Lucent development tools include a
C-compiler, assembler, and run-time library of matrix,
trig, and signal processing functions (DSP32C & DSP3210
Software/Lucent
Applications Library). The CAC support library adds
C-callable functions and a UNIX device driver to control
the VME9U12 board. Several demo and diagnostic utilities
are supplied as examples to quick start your development.
D3BUG, our C-source debugger,
facilitates development of your DSP application software.
VME Backplane Connectors
Only standard VME signals and power pins are used. None
of the A or C rows of P2 or P3 are used.
Back to Diagram
4 TDM Serial Buses
The time-division
multiplexed (TDM) subsystem provides communication
links between DSPs on the baseboard, across multiple
boards, and to the mezzanine subsystems mounted on each
board. FPGA chips control the four buses which are all
clocked at the same rate.
Any DSP or mezzanine board can drive or receive from
any subset of the four TDM
buses. Data flow between DSPs, other boards, and
mezzanine devices is configured by a user's program on
the host.
Back to Diagram
Base Address
Four hex rotary switches set the memory address (A24
standard or A32 extended). Each board occupies 128k bytes
of address space.
Back to Diagram
Optional T1 Line
Interface
This add-on board demultiplexes incoming standard 1.544
Mbps T1 data and multiplexes outbound T1. Both AMI and
NRZ are supported. Cutouts in the front panel provide
access to header pins designed to accept ribbon cables
for connection to the patch
panels. See bottom of page for
details on this add-on board.
Back to Diagram
TDM Expansion
The TDM subsystems of up to 12 VME9U12 boards can be
inter-connected to enable communications between the
resources of all boards. The number of boards that can be
linked depends on the TDM clock rate. The TDM bus can
also be used to communicate with a user's custom board in
another VME slot. The T1D or 9UEXP mezzanine board and
appropriate cables must be present on each board sharing
the TDM bus.
Back to Diagram
Status LEDs
Two rows of LEDs indicate VME activity and programmable
status of each DSP. The SLAVE LED lights during
programmed I/O and MASTER lights during each DMA cycle.
Each of the remaining pairs of LEDs are controlled by
either the DSP or host writing to a reserved memory
location.
Back to Diagram
VME Bus Interface
Both slave (programmed I/O) and master (DMA) modes can be
used to transfer data between the host's and DSP's memory
- 32 bits in a single VME bus access. Slave mode is used
to communicate with non-DSP resources or to access the
DSP's memory as 8, 16, or 32-bit data. A BROADCAST mode
supports simultaneous, write-only, transfers to all DSP
chips on a single board.
Back to Diagram
Vectored Interrupts
By writing to its PIR register, each DSP can generate a
vectored VME interrupt. Control is provided by an
interrupt mask and status register. The DSPs can be
interrupted by the host by asserting either of the
interrupt pins INTREQ1 or 2. These signals are cleared by
the DSP acknowledgement IACK1 or 2.
Back to Diagram
DSP FPGA
Each of six field programmable gate arrays controls a
pair of DSP chips, providing VME address decode, read and
write transfers between the host and each DSP chip,
external interrupt control, TDM interface to the DSPs'
serial ports, and control of the status LEDs.
Back to Diagram
DSP Memory
Each DSP has 6k bytes of internal RAM and a field
upgradable SIMM module containing 512k bytes of private
zero wait-state external static RAM. This memory is
directly accessible by the DSP's program or by the host
via the DSP's parallel port DMA transfers.
Back to Diagram
12 Lucent DSP32C
Processors
Each processor communicates with the host via its
parallel port and with other resources on the board via
its serial port and TDM subsystem. Each DSP is clocked at
an 74 MHz rate yielding 37 MFLOPS and 18 MIPS. The
VME9U12/50 is clocked at 50 MHz.
Back to Diagram
Optional CODEC Interface
(C12 or HC12)
These mezzanine boards provide twelve channels of CD or
toll quality audio A/D and D/A. Cutouts in the front
panel provide access to header pins designed to accept
ribbon cables for connection to the patch panels. See bottom of
page for details on these add-on boards.
Back to Diagram
VME Enable/Disable
Switch
controls the board's ability to respond to or generate
activity on the VME bus. This can be used to isolate the
board while performing host system diagnostics.
Back to Diagram
Reset
A momentary push button provides a hardware reset,
canceling any VME transaction in process and
reconfiguring the programmable gate arrays from an
on-board EPROM.
Back to Diagram
9UEXP
P/N: 9MX1
Unlike the VME6U6, the TDM expansion capability for
the VME9U12 is only available as a mezzanine board
option. The 9UEXP board is a stripped down version of the
9UT1D leaving only the TDM expansion circuitry. This
saves cost for applications that require more
interconnected VME9U12 boards than T1 interfaces.
Specifications
| P/N code |
9V1B
|
9V1C
|
| Clock |
50MHz
|
74MHz
|
12 Lucent DSP32C R35 processors
9U size VME board
Bus master 32-bit DMA transfer
32-bit DMA address ptr, 14-bit word count
Slave memory mapped I/O
32/24 bit addressing (MA32,SA32/24)
32/16 bit data transfer (MD32,SD32/16)
512k byte private SRAM per DSP |
| Size |
9U 400mm
|
| MTBF |
86,000 hours @
40°C
|
| Power |
6A @ 5V
|
Data Transfer Rates:*
DSP to VME via |
|
DMA:
Programmed
I/O: |
2.8 MB/sec
2.8 MB/sec
|
| VME to
DSP via |
|
DMA:
Programmed
I/O: |
2.2 MB/sec
4.0 MB/sec
|
| *(These rates are measured by an
application program running on a Force 20. Actual
speed depends on host computer and size of data
buffer being transferred.)
|
|
