July 31, 2002

Overview

Version 0.0.2 is a preliminary, evaluation release of the DPL3 software. Not all of the DPL3's functionality is implemented in this release.

Currently the hardware FPGA configuration and software supports receiving E3 G.751 E1 payloads with 16 embedded E1 streams.

The "DPL3 Software Reference Manual" and "DPL3 Hardware Reference Manual" describe details of the currently supported and unsupported features.

The following changes are introduced in this release:

• Changes in the API library.

• Changes in the FPGA configuration.

• New naming convention for FPGA configuration files.

• Enhancements to the demonstration programs.

• Enhancements and fixes to the software installation procedure.

• System start-up initialization script is implemented.

Note: This release includes new FPGA configurations. Run the dpl_jtag program to update the FPGAs on the DPL3 boards. (Contact CAC for details).

This release is intended for evaluation purposes and does not represent the intended final production release. Some aspects of the application program interface (API) are subject to change as the software development continues to meet design requirements and usability issues.

Changes in the API library

A problem in the dpl_chan_read is fixed that could cause failure when reading from a channel set to blocking mode when not enough data was available.

The dpl_chanopen_list and dpl_chanopen_mask functions are modified to adjust the latency value to correspond to an integral number of DMA transfers from the board and to insure that the latency adheres to the minimum and maximum limits. The adjustment and limits are dependent on the number of time slots in the channel.

A new function, dpl_chan_latency, provides a method for determining the adjusted latency for a given number of time slots and requested latency.

The source code and header files for the API have been modified to remove unused and obsolete code. Macros and function prototypes not required by channelization applications have been moved to a new header file named dpllib.h. Channelization programs should include dplutil.h. Only diagnostic and special-purpose programs, as well as API source code, need to include dpllib.h.

Changes in the FPGA Configuration

The channel latency scheme is modified such that the channel descriptor now specifies the number of DMAs between notification rather than the number of bytes. The user-level API functions still specify the number of bytes per notification.

A bug is fixed that caused errors at DMA page crossings under certain conditions.

A bug is fixed that caused occasional skipped and/or repeated virtual E1 frames.

Channel DMA queue entries now contain a counter value that can be used to check queue synchronization.

New Naming Convention for FPGA Configuration Files

There are several FPGA configuration types that can be loaded on DPL3 boards depending on the following characteristics:

-	Type of L3 payload to be channelized (E3 G.751-E1, E3 G.751-Raw, DS3, etc.)
-	The VIO level of the PCIbus slot (5 volts or 3.3 volts)
-	Number of FPGAs populated on the DPL3 board (1 or 2)

In addition to the various permutations of those characteristics, FPGA configurations also have associated version numbers.

The FPGA configuration data files are now named according to their characteristics and version numbers as follows.

The primary FPGA configuration files are named:

     dpl3a-TYPE-VP-VERSION.xsvf

The secondary FPGA configuration files are named:

     dpl3b-TYPE-VERSION.xsvf

The TYPE portion specifies the L3 payload type.

e3g751e1	E3 G.751 with 16 virtual E1 framers
l1only	For boards only the quad-L1 framer populated

Currently e3g751e1 is the only available TYPE option.

The VP portion specifies the PCIbus VIO level and FPGA population:

51	5 volt VIO and 1 FPGA populated
52	5 volt VIO and 2 FPGAs populated
31	3.3 volt VIO and 1 FPGA populated
32	3.3 volt VIO and 2 FPGAs populated

The VERSION portion specifies release version of the FGPA configuration which includes integer values for the major, minor and update version numbers.

      Major-Minor-Update

For example, the current release includes the following two FPGA configuration files:

      dpl3a-e3g751e1-51-0-0-2.xsvf
      dpl3a-e3g751e1-52-0-0-2.xsvf
      dpl3a-e3g751e1-31-0-0-2.xsvf
      dpl3a-e3g751e1-32-0-0-2.xsvf
      dpl3b-e3g751e1-0-0-2.xsvf

Enhancements to the Demonstration Programs

The demonstration API is now built as a unix archive library rather than left in separate object files.

The demonstration API includes preliminary code to implement handling of framer status events: enabling of status receive and methods for handling framer errors in the channel read function.

The configuration files for channelization demonstration programs include more options to control buffer size, latency and debug mode.

Code is added to test ITU-T (CCIT) o.153 test patterns. This code must be enabled in the source file if testing for the patterns is desired.

The demonstration programs have also been modified to provide more implementation comments and better display output.

New configuration files are provided for the demonstration programs. They test additional framers and channels.

Enhancements and Fixes to the Software Installation Procedure

The command, make install is now used to install the API, support and diagnostic programs and hardware configuration data into a designated directory tree. See the Installation Instructions for details.

A problem was fixed in the configuration scripts that caused building the dpldebug program to fail if the configure program was invoked using an absolute path name.

Several programs and library modules have been modified to satisfy warnings from the compiler.

System Boot-up Initialization Script is Implemented

The start-up initialization script for DPL3 boards is now functional and invokes the dpl_init program during the system boot process. Installation of the initialization script is done as an optional part of the device driver installation. See the Installation Instructions for details.