October 29, 2004

Overview

The following changes are introduced in this release:

Items Specific to LightParser:

• Fixed E1 sync problem.

• Added 39MHz clock status to hardware and port status program.

• Support for Virtex FPGA types.

Items Specific to DPL3:

None.

General Items:

• Modified computation of latency DMA settings.

• Support for custom version FPGA file names.

• Modified utility programs.

• Modified demonstration programs.

• Changes to FPGA configurations.

• Component versions for this release.

• Known problems.

Notes:

This release includes new FPGA configurations for LightParser boards. Run the dplp_flashup program to update the FPGAs on the boards.

Version 0.6.2 is a beta release of the Channelization API for DPL3 and LightParser Boards. This release does not represent the intended final production release. Some aspects of the application program interface (API) are subject to change as the software development continues to meet design requirements and usability issues.

LightParser: Fixed E1 Sync Problem

The E1 stream framer logic (in the Virtex FPGA) is fixed to properly sync to E1 streams. Previously, the framer could fail to get in sync under certain conditions.

LightParser: Added 39MHz Clock Status to Hardware and Port Status Program

Status bits are added to the Virtex FPGA to provide status of the DCM for the 39 MHz clock. The dplp_portcfg program includes display of the new status information.

LightParser: Support for Virtex FPGA Types

The API new includes support for multiple types of Virtex FPGA configurations. The types include the "standard" type for SDH and PDH parsing and the future "atm" type for SDH parsing with ATM cell delineation and filtering.

Modified Computation of Latency DMA Settings

The code in the host API that determines the DMA settings for a channel is modified to use a wider range of possible settings.

The DMA settings are based on the requested latency for a channel and determine how many data transfers are required before notifying the device driver that new data (or buffer space) is available. The wider range of DMA settings allows the computation to choose settings that can result in actual latencies that are closer to the requested value.

A new error code, CAC_ERR_LATENCYDMA, is introduced. This error will be returned by the channel open functions if usable DMA settings cannot be determined. Normally this should never happen.

The cac_latency_min_bytes and cac_latency_max_bytes functions are modified to return values consistent with the expanded range of DMA settings.

Support for Custom Version FPGA File Names

Support for custom (or customer supplied) FPGA configuration files is added to the API and certain utility programs that deal with FPGA configuration files.

Custom version numbers are those with 4 version parts (e.g. 0-6-2-3) which are based on versions released by CAC. Preliminary support for such file versions had been previously included but was referred to as "OEM" versions. The naming of functions and macros is changed to "CST" for "custom".

Modified Utility Programs

The dplp_flashup and dpl3_flashup programs now allow version numbers for the -v option to be specified with dashes or dots, as well as colons. (e.g. -v0.6 is now acceptable). These programs also support custom version numbers (those with four parts) and custom Virtex FPGA configuration files which will be used for future custom FPGA support on LightParser boards.

The dplp_flashup program includes support for Virtex FPGA types discussed above.

The dplp_init, dpl_init, dplp_info, dpl_info, dplp_find, dpl_find, dplp_jtag and dpl_jtag programs are modified for the new naming of custom version functions and macros.

Modified Demonstration Programs

The dplp_multirec and dpl3_multirec programs are modified to display the adjusted as well as the requested buffer sizes and latencies when the verbose option is specified.

Changes to FPGA Configurations

The LightParser Virtex FPGA includes the following changes:
Modified E1 synchronization state machine to properly handle aysynchronous E1 streams.

Added status bit for 39MHz clock DCM.

Component Versions for This Release

The Channelization API software release includes several components of software and hardware FPGA configurations. All the components have the same major and minor version numbers. However the update version number of each component may vary depending on the number of changes and iterations each component has gone through between general distribution releases.

The component versions for DPL3 and LightParser Software Release 0.6.2 are:

Component:	Version:
API Library and Programs	0.6.2
Solaris Device Driver	0.6.1
Linux Device Driver	0.6.1
LightParser Spartan FPGA Configuration	0.6.3
LightParser Virtex FPGA Configuration	0.6.3
DPL3 Main FPGA Configuration	0.6.0
DPL3 Expansion FPGA Configurations
E3 G751 E1 variation	0.6.0
E3 G832 Bulk variation	0.6.0
DS3 T1 variation	0.6.0
Generic variation	0.6.0

Known Problems

The following problems are known to exist in this release:
• LightParser:

  DS1 extraction is not yet working properly.

• DPL3:

  A problem in the Main FPGA configuration occasionally leaves the board in state which causes transmit channels to timeout on one or or more framers. This situation occurs primarily when the board is initialized and primarily affects the virtual L1 transmit streams. The only work-around is to reinitialize the board using the dpl_init program with its -M option.

  Loss of sync detection from Comet framers is not working properly.

  ESF framing is not yet supported for DS1 extraction from DS3 input.