January 20, 2005

Overview

The following changes are introduced in this release:

Items Specific to LightParser:

• Initial implementation of ATM support.

• Added missing SDH parse path to the API.

• Added local loopback control for the Quad E3/T3 port.

Items Specific to DPL3:

• Implemented ESF multi-frame mode for embedded, receive DS1 streams.

• Added Bulk DS1 channel mode.

• Resolved initialization problems.

General Items:

• Important: update for programming Xilinx Proms.

• Modified utility programs.

• Modified diagnostic programs.

• New or modified demonstration programs.

• Changes to FPGA configurations.

• Component versions for this release.

• Known problems.

Notes:

This release includes new FPGA configurations for LightParser and DPL3 boards. Run the dplp_flashup program to update the FPGAs on the boards.

Version 0.7.0 is a beta release of the Channelization API for DPL3 and LightParser Boards. This release does not represent the intended final production release. Some aspects of the application program interface (API) are subject to change as the software development continues to meet design requirements and usability issues.

LightParser: Initial Implementation of ATM Support

LightParser provides the following functionality for ATM support:
• SDH extraction of C3, C4 and DS3 streams carrying ATM traffic.
• ATM cell delineation and NULL cell deletion.
• Basic cell filtering and tagging based on source and VPI/VCI pairs.
• Hooks for customer-designed cell filter algorithms in HDL.
• Host channelization of the bulk ATM stream after the filter.
• Host channelization of separate filtered and tagged ATM streams.

The ATM cells received by host applications are blocks of 64 bytes containing:

• 48 bytes of payload from the incoming cell.
• 4 bytes of header information from the incoming cell.
• the HEC byte from the incoming cell.
• a status byte generated in the cell filter in the Virtex.
• 2 bytes of source and filter identification, generated in the Virtex.
• 2 4-byte timestamps (high and low resolution) generated in the Virtex.

SDH signal parsing and ATM cell extraction and filtration are done in the Virtex FPGA using a configuration that is separate and distinct from the standard SDH / PDH parsing configuration. Enhancements to the dplp_flashup program provide the means of controlling which Virtex configuration is loaded into each particular board. Support for customer designed ATM filter mezzanine logic is underway and will be included in a future release.

Software changes provide support for bulk ATM channels and an ATM service thread in the device driver which separates ATM cells based on the source and filter ID tags and makes the individually filtered cell streams available to ATM client channels opened by user applications.

New API functions provide the means of configuring the ATM cell filter, controlling the ATM service and opening ATM client channels. Modifications to existing API functions extend their functionality for supporting the ATM parser configuration and channel IO operations.

Some of the library functions for configuring the ATM filter are not yet included in the API. Example code for these operations and sample programs are found in a directory named ATM_info, which is temporarily included in the software distribution archive.

Support for the ATM service device driver thread is currently not available for Solaris.

LightParser: Added Missing SDH Parse Path to the API

The SDH parse path of STM1 to TUG3 to TUG2 to VC2 to DS2 to DS1 was missing from list of supported SDH parse paths. A new macro has been added for this path (PATH_STM1_TUG3_TUG2_VC2_DS2_DS1) and it is included in the various API functions that use parse path macros.

LightParser: Added Local Loopback Control for the Quad E3/T3 Port

The cac_quade3_loopback function can now configure the Quad-E3/T3 port for digital or analog loopback mode. These modes loop the outgoing signals back to the corresponding inputs.

DPL3: Implemented ESF Multi-Frame Mode for Embedded, Receive DS1 Streams

The DPL3 board now supports receiving virtual, embedded DS1 streams (DS1s de-multiplexed from DS3) with ESF multi-frame.

The dpl_init and dpl_framercfg programs configure the virtual DS1 framing logic for D4 multi-frame by default (for DS3 payload configurations). The dpl_framercfg program can be told to configure the DS1 extraction to use ESF multi-frame.

The DS1 multi-frame mode (either D4 or ESF) is controlled via API functions cac_l3_set_mode and cac_l3_init. When the mode or l3_opts argument to these functions include the bit defined as L3_DS1_ESF the DS1 framing logic in the FPGA is set to use ESF mode. Otherwise it is set for D4 multi-frame mode. This controls the multi-frame mode used when searching for synchronization in the DS1 streams embedded in a DS3 and when generating the multi-frame for outgoing DS1 streams multiplexed up to DS3.

Note that ESF multi-frame does not yet work properly for transmitted DS1 streams that are multiplexed up to DS3. ESF does work for both receive and transmit DS1 streams using the Comet framers.

DPL3: Added Bulk DS1 Channel Mode

Full DS1 streams can now be received in a mode called DS1 Bulk, which means each frame of the incoming DS1 stream is received as a block of 32 bytes. The first 24 bytes contain the data from the 24 DS1 time slots. The 25th byte contains the 193rd DS1 framing bit in bit 7. The remaining data is currently unused.

Future enhancements may include multi-frame and non-aligned frame markers making it easier for host applications to extract signaling data from DS1 streams.

This mode is only available with the cac_chanopen_stream function by specifying the modes argument as CAC_CHAN_MODE_DS1_BULK | CAC_CHAN_MODE_DS1_RCV.

DPL3: Resolved Initialization Problems

Various problems could arise after the a DPL3 board is initialized or FPGAs are reconfigured. The most notable problem was timeouts when attempting to read or write Comet or embedded L1 channels.

Most of these problems have been resolved through a combination of modifications to FPGA logic and changes in software that initializes or configures the board.

One problem that remains appears on rare occurrences after the Expansion FPGA is configured. The problem is failure of the framing logic for the E1 or DS1 streams de-multiplexed from E3 or DS3. The failure is eliminated by reconfiguring the Expansion FPGA using the dpl_init program with the -E@ or -R option.

Important: Update for Programming Xilinx Proms

New DPL3 and LightParser boards are built with Xilinx FPGA configuration Proms fabricated by a new semiconductor source. The Proms are used to store the configuration data for the host interface FPGA on DPL3 and LightParser boards.

The new Xilinx Proms have different timing requirements for programming which require new configuration files and software. They cannot be safely programmed using the software and configuration files distributed with previous DPL3 and LightParser software releases. The new versions of the software (dplp_flashup and dpl_flashup programs) include a compatibility check of the board's Xilinx Prom type and the configuration data file. But previous software versions do not have this check. The older boards are compatible with both the old and new software and configuration files.

Attempting to load XSVF configuration files on the newer DPL3 or LightParser boards with configuration file versions below 0.7.1 or using software prior to release 0.7.0 could result in the configuration information being lost and the board will no longer function. If this occurs, it will be necessary to use the Xilinx iMPACT software to restore the FPGA configuration data through a JTAG programming pod.

The affected boards (with the newer Xilinx prom) are DPL3 boards with serial numbers greater than 50100028 and LightParser boards with serial numbers greater than 14700027.

Modified Utility Programs

The dpl_init, dplp_init programs are modified to check the status of the clock DLL in the Main and Expansion FPGAs on DPL3 boards and in the Spartan FPGA on LightParser boards. A DLL is reset and re-checked if it is not locked.

The dpl_init program includes additional changes for DPL3 boards:

• Added enabling of the Expansion interface in the Expansion FPGA. This is required because the FPGA now comes up with it disabled.
• The interface between the Main and Expansion FPGAs is left disabled during the initialization process until the channelization control has been enabled.
• The default framer modes for DS3 and DS1 payloads are changed to use C-Bit Parity format for DS3, D4 multi-frame for DS1 streams multiplexed in the DS3 signal, and ESF multi-frame for the Comet framers.

The dplp_flashup, dplp_jtag, dpl_flashup and dpl_jtag programs have added checking compatibility between XSVF configuration data file and the version of the Xilinx Prom on DPL3 or LightParser boards.

The dpl_serial and dplp_serial programs are modified to include settings for the Xilinx Prom type in a new EEROM word used for storing hardware Assembly Options.

The dpl_info and dplp_info programs are modified to display the new Assembly Options.

The dplp_info program for LightParser is modified to include the Virtex FPGA configuration type for the board. Currently this will be either standard or atm.

The dplp_streams program for LightParser now includes support for configuring C-3 and C-4 transmit and ATM (bulk) receive streams. It can also display status of ATM streams and options.

The dplp_portstat program for LightParser now includes status of the Quad-E3/T3 port and is fixed to poroperly report when the CMI electrical port is the selected reference clock.

The dplp_virtexcfg program for LightParser is deprecated. The dplp_flashup and dplp_init programs are the preferred methods for loading the Virtex FPGA. It is still included in the distribution and built, for now, but its functionality is somewhat reduced. It can only be used to load a specified Virtex configuration file or reconfigure the Virtex FPGA from flash (on boards equipped with the Flash memory). It no longer searches for newer Virtex configuration file versions.

The dpl_framercfg program for DPL3 includes the following changes and additions:

• The use of the -V option is expanded and requires a parameter with one or more codes to enable or disable the Virtual framers, set ESF or D4 multi-frame mode for embedded DS1 streams, and to gather and display sync status of virtual framers.
• A new -W option has the program check for the L3 framer being in frame. It will retry several times, pulsing the the framer's RESYNC control.
• The -x and -4 options for specifying multi-frame modes for the Comet framers have been replaced with a new -m option that takes one or more parameter codes to specify the multi-frame modes.
• ESF multi-frame is now the default for the Comet framers in T1 mode. D4 is the default for the virtual DS1 framers.
• If the DS3 framing format for the L3 framer is not specified, C-Bit parity mode will be used by default unless the framer is currently in sync and indicates it is not receiving C-Bit framing, in which case M13 framing formation is used.
• The parameter for turning off loop-back in the Comet framers with the -l option is changed from o to n.

Modified Diagnostic Programs

The dplp_alloctest program is modified to include ATM channel types and a set of commands for controlling the ATM service.

The dplp_recv program is modified to support ATM bulk and client channel types. Both the dpl_recv and dplp_recv programs are modified to use the -T option to set a permanent timeout value and to add a new -Z option to specify an initial timeout value.

The dpl_chantest and dplp_chantest programs include the following changes:

• The generation and checking of ITU patterns is made more efficient by minimizing the use of modulus division.
• Enabling transmit channels is held off until the channel buffer is half full to avoid underflows when many channels are being started.
• Receive channels are allowed up to 3 overflow errors before any data is read to accommodate possible overflows while waiting for framer sync.

The dpl_memtest and dplp_memtest programs are modified to set the exit value to 1 if any number of errors occur.

New or Modified Demonstration Programs

The new dplp_atmclient program demonstrates how to open and read ATM client channels as well as how to configure and control the ATM service.

Example programs for configuring the SDH parser and ATM filter with the ATM version of the LightParser Virtex have not yet been integrated into the regular software distribution. They are found in a directory named ATM_info, which is temporarily included in the software distribution archive.

The

dplp_streamstat program has a new -L option which forces the reference clock to be the local clock when the parser is configured.

Changes to FPGA Configurations

The LightParser Spartan FPGA includes the following changes:
• The XSVF file is built with new tool set for compatibility with the new Xilin prom programming requirements.
• Fixes for ATM stream logic that was included but not tested in the previous release.

The LightParser Virtex FPGA for standard SDH / PDH processing includes the following changes:

The only change in this FPGA is to update the version number for 0.7.x compatibility.

The LightParser Virtex FPGA for ATM processing includes the following changes:

This is the first official release of the ATM Virtex variation. DS3 framing has been added since the previous pre-release.

The DPL3 Main FPGA includes the following changes:

• The XSVF files are built with new tool set for compatibility with the new Xilin prom programming requirements.
• The interface with the Expansion FPGA is now disabled when the FPGA is initially configured.
• Logic is added for clearing the ram-based logic of the Comet interface.
• The startup logic reset, suspected of causing some of the initialization problems, has been removed.

The DPL3 Expansion FPGAs include the following changes:

• The DS3 payload version includes logic to implement ESF multi-frame mode for the DS1 streams extracted from DS3 input.
• The interface with the Main FPGA is now disabled when the FPGA is initially configured.
• Logic is added for clearing the ram-based framing logic as part of the framer resynchronization operation.
• Added auto reset of the clock DLL at startup and the startup logic reset, suspected of causing some of the initialization problems, has been removed.
• Various changes to clear and reset operations that resolved some initialization problems.

Component Versions for This Release

The Channelization API software release includes several components of software and hardware FPGA configurations. All the components have the same major and minor version numbers. However the update version number of each component may vary depending on the number of changes and iterations each component has gone through between general distribution releases.

The component versions for DPL3 and LightParser Software Release 0.7.0 are:

Component:	Version:
API Library and Programs	0.7.0
Solaris Device Driver	0.7.0
Linux Device Driver	0.7.0
LightParser Spartan FPGA Configuration	0.7.1
LightParser Virtex FPGA Configurations
Standard SDH/PDH variation	0.7.0
ATM variation	0.7.3
DPL3 Main FPGA Configuration	0.7.2
DPL3 Expansion FPGA Configurations
E3 G751 E1 variation	0.7.2
DS3 T1 variation	0.7.2
E3 G832 Bulk variation	0.7.0
Generic variation	0.7.0

Known Problems

The following problems are known to exist in this release:
• LightParser:

  Data corruption has been reported when recording raw, descrambled STM-1 signals that include AU3s.

  Using the clock extracted from the electrical (CMI) port causes some data corruption. Work-around is to use the local clock reference when receiving electrical STM-1.

  The ATM version of the Virtex is not able to frame DS3 streams from SDH streams. A work-around is to route the raw DS3 streams from SDH input through the Quad-T3 port, loop the signal back in and frame the DS3s from the Quad-T3 input.

  Detection of ATM client channel overflow (pointers to the bulk ATM buffer that are no longer valid) is not yet implemented in the ATM service.

• DPL3:

  ESF framing is not yet supported for transmitting DS1 streams multiplexed to the output DS3 signal.

  Possible failure of framing logic for embedded E1 or DS1 streams after configuration of Expansion FPGA. See the discussion of this topic in previous notes for details.