February 14, 2005
Overview
The following changes are introduced in this release:
Items Specific to LightParser:
Items Specific to DPL3:
General Items:
Notes:
Version 0.7.1 is a beta release of the Channelization API for DPL3 and LightParser Boards. This release does not represent the intended final production release. Some aspects of the application program interface (API) are subject to change as the software development continues to meet design requirements and usability issues.
LightParser: Initial Implementation of Adjustable E1 Transmit Rates
dplp_flashup -uv -xR dplp0
The LightParser API includes new functions to initialize the rate control tables and adjust the transmit rates.
For more information, please see information and sample code
in the in the RATE_info directory of the software distribution.
DPL3: New and Modified Framer Control API Functions
A new function named cac_l3_get_modes retrieves the current configuration settings for all 3 of the L3 interface devices. A new function named cac_l3_get_status retrieves the current status information for the L3 interface devices. Those two functions replace the three functions, cac_l3_get_mode, cac_liu_get_mode and cac_jat_get_mode, which are no longer included in the API. Many of the macros for L3 configuration options and status information have also changed.
The old cac_l3_get_status for reading the FPGA framer status registers is replaced by cac_fpga_framer_status(). This new function provides additional status information such as the currently enabled receive and transmit framers.
The embedded documentation for the framer control functions has been enhanced to include better descriptions and a list of the macros available for specifying configuration modes and interpreting status results.
Changes to FPGA Configurations
Component Versions for This Release
The component versions for DPL3 and LightParser Software Release 0.7.1 are:
| Component: | Version: |
| API Library and Programs | 0.7.1 |
| Solaris Device Driver | 0.7.0 |
| Linux Device Driver | 0.7.0 |
| LightParser Spartan FPGA Configuration | 0.7.1 |
| LightParser Virtex FPGA Configurations | |
| Standard SDH/PDH variation | 0.7.0 |
| Experimental SDH/PDH variation w/ E1 XMT rate adjust | R.9 |
| ATM variation | 0.7.3 |
| DPL3 Main FPGA Configuration | 0.7.2 |
| DPL3 Expansion FPGA Configurations | |
| E3 G751 E1 variation | 0.7.2 |
| DS3 T1 variation | 0.7.2 |
| E3 G832 Bulk variation | 0.7.0 |
| Generic variation | 0.7.0 |
Data corruption has been reported when recording raw, descrambled STM-1 signals that include AU3s.Using the clock extracted from the electrical (CMI) port causes some data corruption. Work-around is to use the local clock reference when receiving electrical STM-1.
The ATM version of the Virtex is not able to frame DS3 streams from SDH streams. A work-around is to route the raw DS3 streams from SDH input through the Quad-T3 port, loop the signal back in and frame the DS3s from the Quad-T3 input.
Detection of ATM client channel overflow (pointers to the bulk ATM buffer that are no longer valid) is not yet implemented in the ATM service.
ESF framing is not yet supported for transmitting DS1 streams multiplexed to the output DS3 signal.Possible failure of framing logic for embedded E1 or DS1 streams after configuration of Expansion FPGA. See the discussion of this topic in previous notes for details.