March 3, 2005
Overview
The following changes are introduced in this release:
Items Specific to LightParser:
Items Specific to DPL3:
General Items:
Notes:
Version 0.7.2 is a beta release of the Channelization API for DPL3 and LightParser Boards. This release does not represent the intended final production release. Some aspects of the application program interface (API) are subject to change as the software development continues to meet design requirements and usability issues.
DPL3: Modified Framer Control API Functions
The macros for Comet framer transmit loop timing mode, E1_TX_LOOP_TMG and T1_TX_LOOP_TMG, are removed because the DPL3 hardware does not directly support the Comet framers being configured in that way. The functionality for this mode does exist by using the cac_comet_txclock function to have the FPGA use the receive clock as the transmit clock.
Comet configuration functions are fixed to properly set the Comet framer transmit timing registers. The changes include removing changes to the transmit clock selection from the cac_comet_loopback function. This function now only addresses the loop-back control in the framers. The dpl_framercfg program is modified to set the appropriate transmit clock source for the loop-back mode selected.
Some of the Comet framers and L3 interface API functions are fixed to set an appropriate error code in the global errno variable in cases where this was not previously done.
The programmer reference manual for the DPL3 now includes documentation for the Comet and L3 interface API functions.
DPL3: Bug Fix in the Board Initialization Program
DPL3: Corrected Expansion FPGA Configuration
Fixed Default Timeout Chosen by Linux Device Driver for Raw (unframed) E1 Channels
Component Versions for This Release
The component versions for DPL3 and LightParser Software Release 0.7.2 are:
| Component: | Version: |
| API Library and Programs | 0.7.2 |
| Solaris Device Driver | 0.7.0 |
| Linux Device Driver | 0.7.1 |
| LightParser Spartan FPGA Configuration | 0.7.1 |
| LightParser Virtex FPGA Configurations | |
| Standard SDH/PDH variation | 0.7.0 |
| ATM variation | 0.7.3 |
| Experimental SDH/PDH variation w/ E1 XMT rate adjust | R.9 |
| DPL3 Main FPGA Configuration | 0.7.2 |
| DPL3 Expansion FPGA Configurations | |
| E3 G751 E1 variation | 0.7.2 |
| DS3 T1 variation | 0.7.2 |
| E3 G832 Bulk variation | 0.7.0 |
| Generic variation | 0.7.1 |
Data corruption has been reported when recording raw, descrambled STM-1 signals that include AU3s.Using the clock extracted from the electrical (CMI) port causes some data corruption. Work-around is to use the local clock reference when receiving electrical STM-1.
The ATM version of the Virtex is not able to frame DS3 streams from SDH streams. A work-around is to route the raw DS3 streams from SDH input through the Quad-T3 port, loop the signal back in and frame the DS3s from the Quad-T3 input.
Detection of ATM client channel overflow (pointers to the bulk ATM buffer that are no longer valid) is not yet implemented in the ATM service.
ESF framing is not yet supported for transmitting DS1 streams multiplexed to the output DS3 signal.Possible failure of framing logic for embedded E1 or DS1 streams after configuration of Expansion FPGA. See the discussion of this topic in previous notes for details.