March 11, 2005

Overview

The following changes are introduced in this release:

Items Specific to LightParser:

None.

Items Specific to DPL3:

None.

General Items:

• New API function to determine PCI slot location.

• Modified utility programs.

• Component versions for this release.

• Known problems.

Notes:

Version 0.7.3 is a beta release of the Channelization API for DPL3 and LightParser Boards. This release does not represent the intended final production release. Some aspects of the application program interface (API) are subject to change as the software development continues to meet design requirements and usability issues.

New API Function to Determine PCI Slot Location

The new cac_get_pci_location function will return the PCI bus, device and function numbers for an open DPL3 or LightParser board. This information can be used to determine which physical board in the system corresponds to the open device. This is most useful on Linux where the board instance numbers can change when boards are added, removed or moved in the system.

Modified Utility Programs

The dpl_info, dplp_info, dpl_find, and dplp_find programs are modified to include reporting of the PCI slot location of each board.

The dpl_find program is also modified to report the T1 and T3 clock rates (instead of the E1 and E3 rates) for boards with DS3 L3 payload configurations.

Component Versions for This Release

The Channelization API software release includes several components of software and hardware FPGA configurations. All the components have the same major and minor version numbers. However the update version number of each component may vary depending on the number of changes and iterations each component has gone through between general distribution releases.

The component versions for DPL3 and LightParser Software Release 0.7.3 are:

Component:	Version:
API Library and Programs	0.7.3
Solaris Device Driver	0.7.2
Linux Device Driver	0.7.2
LightParser Spartan FPGA Configuration	0.7.1
LightParser Virtex FPGA Configurations
Standard SDH/PDH variation	0.7.0
ATM variation	0.7.3
Experimental SDH/PDH variation w/ E1 XMT rate adjust	R.9
DPL3 Main FPGA Configuration	0.7.2
DPL3 Expansion FPGA Configurations
E3 G751 E1 variation	0.7.2
DS3 T1 variation	0.7.2
E3 G832 Bulk variation	0.7.0
Generic variation	0.7.1

Known Problems

The following problems are known to exist in this release:
• LightParser:

  Data corruption has been reported when recording raw, descrambled STM-1 signals that include AU3s.

  Using the clock extracted from the electrical (CMI) port causes some data corruption. Work-around is to use the local clock reference when receiving electrical STM-1.

  The ATM version of the Virtex is not able to frame DS3 streams from SDH streams. A work-around is to route the raw DS3 streams from SDH input through the Quad-T3 port, loop the signal back in and frame the DS3s from the Quad-T3 input.

  Detection of ATM client channel overflow (pointers to the bulk ATM buffer that are no longer valid) is not yet implemented in the ATM service.

• DPL3:

  ESF framing is not yet supported for transmitting DS1 streams multiplexed to the output DS3 signal.

  Possible failure of framing logic for embedded E1 or DS1 streams after configuration of Expansion FPGA. See the discussion of this topic in previous notes for details.