March 8, 2006

Overview

The following changes are introduced in this release:

Items Specific to LightParser:

• Modified handling of status errors in the cac_if_set_rx_mode function.
• Fixed problem with clearing simulation modes.

Items Specific to LightParser2:

• New and fixed optical port status and interrupts.
• Improvements to the PCI interface.
• Reorganization of host control memory regions.
• Initial support for packet mode channels.

Items Specific to DPL3:

• Minor modifications to dpl_framercfg program.

General Items:

• Modifications to API headers and function library.
• Modified utility programs.
• Modified diagnostic programs.
• Updates to software configuration and installation.
• Component versions for this release.
• Known problems.

LightParser: Modified Handling of Status Errors in the cac_if_set_rx_mode Function

The cac_if_set_rx_mode function is modified to not perform post-configuration status checks if the RX_MODE_IGNORE_LOCK_ST flag is included in the options argument.

Previously, this flag only meant that the function would ignore loss of lock or signal when checking status prior to setting the configuration modes but it would return an error if there were errors after the modes were set.

LightParser: Fixed Problem with Clearing Simulation Modes

The cac_chan_sim_clr API function is modified to not clear some of the old simulation mode registers to avoid problems that were affecting some aspects of stream transfers across the Virtex-Spartan interface. This function is only by the dplp_init program and initialization routines in some of the diagnostic programs. The problems were signification when attempting to use dplp_chantest to verify parser and stream configurations.

LightParser2: New and Fixed Optical Port Status and Interrupts

Problems with STM-1 synchronization on optical port B are fixed in the FPGA. Other configuration issues are resolved by reseting the framer and clock synthesizer components when the board is initialized with lp2_init.

The framer and payload aligner status is now implemented in the FPGA and the lp2_portstat program. In addition, new latched status information is available for the CDR and SFP components of the optical ports. The latched status bits remain set until cleared by writing to the register with the bits to be cleared set to 1 in the data written. A new function, cac_if_clr_status is provided in the API for this purpose.

New FAS error monitoring is implemented similar to the B1 and B2 error rate monitor. Logic in the FPGA counts the number of FAS errors and frames. Their values can be read and cleared using the API functions, cac_get_faserr and cac_clr_faserr.

The lp2_portstat program is modified to support the new status information. Modifications to the lp2_portstat program include:

• Status for receive and transmit are displayed on separate lines unless the new -w (wide mode) option is specified.
• The diagnostic information (signal rates, optical power, SFP temperatures, etc.) are displayed by specifying the -d or -D option rather than by default.
• The program clears latched status bits which are set by default. A new -l option is provided to request that they not be cleared.
• The FAS error rates are included when BER values are displayed by specifying the -b option.
• The -B option is now used (in place of -B) to request the BER and FAS counts be cleared.
• The -c option is now used (in place of -m) to display the current configuration settings.

New host interrupt sources are added to provide notification of optical port status events. The FPGA provides separate interrupts for the two optical ports. For each port there is a mask register to specify which of the latched port status events are eligible to generate a host interrupt. The new cac_if_irq_enable function provides the ability to set and read the port interrupt mask and enable notification of an interrupt via software signal.

LightParser2: Improvements to the PCI Interface

Timing improvements in the PCI target logic resolve problems with receiving burst transfers.

The PCI master logic now supports read access, allowing DMA transfers from the host. This is a preliminary step toward supporting transmit channels.

LightParser2: Reorganization of Host Control Memory Regions

Memory regions for the I/O port control registers, channel descriptors and channel buffer page table are reorganized for various reasons. The changes are are, for the most part, transparent but they do create an incompatibility between old and new versions of the software and the FPGA.

The I/O port registers are rearranged to provide for more consistent expansion as feature implementations are added to the design. The division between level 1 and higher level channel descriptors is moved to allow for more level 1 streams (E1, DS1, etc) as those streams are supported. The number of buffer page table entries is reduced to make the FPGA resources available for other purposes. There are still enough entries to handle up to a total of 2 gigabytes for channel buffers.

LightParser2: Initial Support for Packet Mode Channels

This release includes a preliminary implementation of packet mode receive channels. The purpose is to provide a mechanism to support POS, HDLC and ATM streams. The logic and code in the device driver provides a way to handle interrupt queue entries that specify a partial latency amount. These are called "flush queue entries" and allow the host to be notified of the end of a packet being transfered into the channel buffer.

Currently, the only use of the packet channels is the test and demonstration logic in the FPGA. It is used by the new lp2_pktest demonstration program and the lp2_queuetest program includes a command to test the flush queue entries.

DPL3: Minor Modifications to the dpl_framercfg Program

The program includes the following modifications:
• The embedded (virtual) E1 or T1 transmit framers are now enabled or disabled along with the embedded receive framers when the -Ve or -Vd options are used.

• The display of E3 status (when the -S option is used in E3 mode) is rearranged to show the LOF status before the AIS status.

Modifications to the API Headers and Function Library

New Functions for Formatting Large Numbers:
Two functions are added to the utility module of the API to convert large numbers to strings in humanized, decimal format with commas separating the orders of magnitude.

The cac_format_decimal_32 function converts numbers represented in 32 bits (eg uint_32) and cac_format_decimal_64 converts numbers represented in 64 bits (eg uint64_t). Both functions are passed a pointer to a character, to which the converted string is written, and a size to specify how many bytes are available in the array.

Renamed Interrupt Mask / Status Macros:

The macros for the host interrupts corresponding to the bits in the IRQ mask and status registers are renamed to be consistent with the macros used in the device driver code. The new names start with "CAC_IRQ_" instead of "INT_STATUS_", for example, the macro INT_STATUS_L3FRAMER is now CAC_IRQ_L3FRAMER. The exception is the INT_STATUS_ERRSTAT macro which is now CAC_IRQ_HWERR.

Renamed error code macro:

The error code for an invalid or uninitialized MMC is changed from CAC_ERR_INVAL_MMC_MAGIC to CAC_ERR_MMC_INVAL_MAGIC.

Work-around in LightParser2 I2C Functions::

Dummy-reads are added to the cac_i2c_read and cac_i2c_write functions as a work-around for problems with back-to-back accesses of the NE1619 Voltage and Temperature monitor device on LightParser2 boards.

Modified Utility Programs

Aside from any changes to programs mentioned above, this release includes the following changes to utility programs:

The lp2_flashup program can now use the -N option in conjunction with e-u option to update an existing directory entry with a new FPGA type.

Modified Diagnostic Programs

Aside from any changes to programs mentioned above, this release includes the following changes to diagnostic programs:

The dplp_chantest program is modified to support gapped payload stream ID numbering for raw E1 and DS1 streams.

The lp2_memtest program now allows burst transfer mode for the MMC buffer region.

The lp2_dmatest program is modified to support the DMA transfers to the host (from the board) and does so by default.

The lp2_vtmon program has a new display format and checks readings against user-settable voltage tolerance and maximum temperatures. It also has a new option to blink the LEDs for visual testing.

The dpl_alloctest, dplp_alloctest and lp2_alloctest programs are modified to support limited readline capability. Command line editing and history is supported but the programs do not save command history across sessions.

Updates to Software Configuration and Installation

The configuration scripts now recognize the "x86_64" CPU type for systems with Intel x86 EMT64 processors. When the 64-bit variant of Red Hat Enterprise Linux 4 (the tested OS) is installed, the GCC compiler is configured to generate 64-bit code without requiring special command line options. The default configuration will generate 64-bit code for the API and support programs as well as for the device driver. If it is desired to compile the API and applications as 32-bit code on 64-bit Linux platforms, the CFLAGS environment variable must be set to specify the appropriate compiler flags to over-ride the defaults.

For 64-bit Solaris only the device driver is compiled as 64-bit code. If it is desired to compile the API and applications as 64-bit code on 64-bit Solaris platforms, the CFLAGS environment variable must be set to specify the appropriate compiler flags to over-ride the defaults.

These 64-bit compilation issues are described in the 64-bit compatibility section of the installation instructions which are available on the CDROM or the CAC website.

The software configuration option for Linux or Solaris to specify using the readline library installed on the system is changed. The new command line argument to the configure script for this option is --with-readline=system.

Component Versions for This Release

The Channelization API software release includes several components of software and hardware FPGA configurations. The "HW Support" versions are the version numbers for the software support of the particular board or FPGA configuration type.

The API and device driver components have the same major and minor version numbers. Similarly, the "HW Support" versions have the same major and minor version numbers as the corresponding FPGA or FPGA type. However the update version number of each component may vary depending on the number of changes and iterations each component has gone through between general distribution releases.

The component versions for Software Release 0.8.1 are:

Software Components	Version
API Library and Programs	0.8.1
Solaris Device Driver	0.8.1
Linux Device Driver	0.8.1
Hardware Components	FPGA Version		Support Version
LightParser Spartan FPGA Configuration	0.7.1		0.7.1
LightParser Virtex FPGA Configurations
Standard SDH/PDH variation	0.7.0		0.7.0
ATM variation	0.7.3		0.7.3
SDH/PDH Transmit variation	n/a		n/a
LightParser2 Virtex FPGA Configurations
Standard SDH variation	0.2.1		0.2.1
LightParser2 Boot FPGA Configuration	0.0.1		0.0.1
DPL3 Main FPGA Configuration	0.7.3		0.7.3
DPL3 Expansion FPGA Configurations
E3 G751 E1 variation	0.7.2		0.7.2
DS3 T1 variation	0.7.2		0.7.2
E3 G832 Bulk variation	0.7.0		0.7.0
Generic variation	0.7.1		0.7.3

Known Problems

The following problems are known to exist in this release:
• LightParser:

  NDFs, announced and unannounced, are not properly handled in TU-12s. This problem is resolved in an experimental, pre-release FPGA configuration, version f.28, included in the distribution. To load this configuration run the dplp_flashup program as shown below:

              dplp_flashup -uv -xf dplp0
      

  Data corruption has been reported when recording raw, descrambled STM-1 signals that include AU3s.

  Using the clock extracted from the electrical (CMI) port in STM-1 mode causes some data corruption. Work-around is to use the local clock reference when receiving electrical STM-1.

  The ATM version of the Virtex is not able to frame DS3 streams from SDH streams. A work-around is to route the raw DS3 streams from SDH input through the Quad-T3 port, loop the signal back in and frame the DS3s from the Quad-T3 input.

  Detection of ATM client channel overflow (pointers to the bulk ATM buffer that are no longer valid) is not yet implemented in the ATM service of the device driver.

• LightParser2:

  The command fifo for PCI-to-SDRAM transfers is susceptible to overflows during high-rate transfers. In addition PCI-to-SDRAM writes can interfered with DMA transfers. These problems are being investigated and the host interface to SDRAM is currently only used for diagnostic purposes.

• DPL3:

  ESF framing is not yet supported for transmitting DS1 streams multiplexed to the output DS3 signal.

  Possible failure of framing logic for embedded E1 or DS1 streams after configuration of Expansion FPGA. See the discussion of this topic for details.

• Solaris 10 Intel Support:

  The device driver for DPL3, LightParser and LightParser2 boards does not work on the Intel variant of Solaris 10. The problem involves allocating DMA memory for channel buffers.

  Solaris is currently supported on Intel platforms up through Solaris 9. Solaris 10 is supported on Sparc platforms.