October 5, 2004
Overview
The following changes are introduced in this release:
Note:
This release includes new embedded application code.
Run the dpflashup program after installation to update
the embedded code on the DPT4 board(s).
Problem with E1 Signaling Fixed
Problems Fixed in the Linux Device Driver
Code is added to the channel read routines to indicate that no data was
transfered when waiting for available data times out.
Previously it was possible for a read to retry indefinitely if the timeout
occurred on the first transfer for a given read operation.
Several modifications are made to reduce the stack usage in the driver.
This has not been a problem until recent versions of Kernel, including
the Kernel distributed with Red Hat Enterprise Linux 3.
Added 66 MHz PCI Clock Disable Assembly Option
To avoid these problems when used in host systems with a 66 MHz PCI clock,
the DPT4 boards require a modification to force the PCI bus clock to run
at 33 MHz.
New DPT4 boards will be shipped with this modification.
Customers with exisiting boards that are to be run in systems with 66MHz
PCI slots should contact CAC to request an RMA to have the modification
done as a repair item or for details on how to perform the modification.
Boards that have this modification are identified with an assembly option
flag stored in the EEROM on the board.
New versions of the dpinfo and dpserial programs indicate
boards that have this modification as part of the "assembly options"
category.
For older versions of these programs that do not include "PCI66MHz" on
the display line for assembly options, the setting can be determined by
running the dpserial program with the -v option to display the
data contents of the EEROM.
The PCI66MHz flag is located in 4th bit of the 10th word of the EEROM.
This is the third group of 4 hexadecimal values on the line beginning
with "08:".
If the 3rd digit of that group is a 1, the board has been identified
as having the modification.
Additions and Modifications to the API Library
Newer systems that can perform reads much quicker are likely to reach the old
limit and assume incorrectly that the retry data pattern is the correct data.
This problem had been causing system errors when the data being read was
used to indicate buffer addresses on the board.
A new function, pci_up_dma16b, is added to the API for
uploading arrays of 16-bit objects via DMA.
The pci_read_chan function is fixed to set the value of errno
for cases where the error code is provided by the embedded application.
Modifications to Diagnostic and Demonstration Programs
The dpinfo and dpserial programs now include indication
of the board's PCI 66MHz disable assembly option.
The dpserial program includes the ability to set this option.
The dp54xdiag program is fixed to always initialize the framers.
It used to not initialize them when DSP TDM loop-back mode was selected.
The dpdmaxfer program includes testing of the new pci_up_dma16b
API function.
The program is also modified to use _dpstrerror() for reporting error codes
and has two new command line options:
-q to suppress the display of details after the first test iteration.
The dpchantest program now ignores timeouts that occur the first
time a receive channel is read.
It is also fixed to use a separate flag for each receive thread to indicate
that the first word should be ignored when the sync header is suppressed.
The program also has some additional command line options:
-Z delay between opening and starting each transmit and receive thread.
The dprec program is fixed to properly detect loss of sync and
is modified to use _dpstrerror() for reporting error codes.
The dpreceive example program code is fixed to properly
detect loss of sync and to use _dpstrerror() for reporting error codes.
The new version of the embedded MIPS application fixes a bug in saving
data from the Comets' signaling registers in E1 mode.
Reading signaling channels from E1 streams now returns the correct data.
Problems having to do with semaphores protecting the DMA data structures
in re-entrant functions have been fixed in the Linux device driver.
Most of these problems only caused trouble when running an SMP-enabled Kernel
where concurrency is more of an issue.
The PCI data transfer logic of the DPT4 includes a work-around for
bugs in the PCI interface chip used on the board.
The work-around is designed to operate with the PCI at at 33 MHz
and problems can occur if the PCI clock runs at 66 MHz.
In some cases the problems cause the host system to lock up.
The read access retry limit is increased from 15 to 100 to compensate
for some new host systems that are able to perform PCI read accesses
much quicker and more often.
Explanation:
The work-around for bugs in the PCI interface chip used on the DPT4
board includes a retry data pattern.
When the board is unable to respond to a read access from the host system
within a minimum number of PCI clocks, a special "retry" data pattern is
returned.
The API, as well as the device drivers, check for the pattern and retry
the access.
Accesses are retried until the retry pattern is not seen or the retry limit is
reached in which case it is assumed that the retry pattern is actually the
data being read from the board.
-d to specify a delay between test iterations and between each
DMA read within the batch mode iterations.
-T Use the upper byte of each 32-bit word of test data as a tag
to indicate which framer it is for.