July 28, 2011

Overview

The following changes are introduced in this release:

• New assembly option for MIPS speed grade.

• Update for the device drivers.

• Component versions for this release.

• Known issues.

Note:

This release is primarily an update to identify the MIPS processor assembly option for DPT5 and DPT6 boards. It also includes a minor update for the Linux, Solaris and 32-bit Windows device drivers.

New Assembly Option for MIPS Speed Grade

The DPT5 and DPT6 board serialization information now includes a new assembly option to specify the speed grade of the MIPS processor.

Beginning in the Fall of 2011 DPT5 and DPT6 board assembly may transition from 133MHZ MIPS processors to the 100MHz parts used on the original, DPT4 design. The DPT applications never took advantage of the potential performance increase offered by the 133 MHz parts. Therefore, there is no performance impact involved in the changeover.

The dpserial program is modified to query about the MIPS population and both the dpserial and dpinfo programs are modified to display the setting of this option.

A new configuration file is used to configure the clock generator as required for the 100MHz MIPS. and the dpclock program is modified to use the correct configuration file based on the MIPS speed grade option.

Update for the Device Drivers

The Linux, Solaris and 32-bit Windows device drivers in this release include a fix for a problem that could occur with the MIPS trace and debug messages provided by the "virtual serial port" facility and accessed via the dpcons program.

Under certain circumstances the pointers to the circular message buffer maintained in the board's memory and used in the device driver might be left uninitialized or corrupted. This, in turn, can cause incorrect or run-away memory access when the dpcons program is used.

The device drivers are modified to check the validity of these buffer pointers before attempting to use them to access the message storage on the board. Note: the device driver for 64-bit Windows does not currently support the "virtual serial port" facility. So the problem does not exist in the case.

Component Versions for This Release

The DPT software release includes several components of software, embedded code and hardware FPGA configurations. The major and minor version numbers are the same within each category. However the update version number of each component may vary depending on the number of changes and iterations each component has gone through between releases.

The components and their versions for DPT Software Release 1.5.9 are:

Software Components		Version
	API Library and Programs	1.5.7
	Linux Device Driver	1.5.8
	Solaris Device Driver	1.5.5
	32-bit Windows Device Driver	1.5.3
	64-bit Windows Device Driver	1.5.0
Embedded Code Components
	Embedded MIPS Loader	1.4.0
	Embedded MIPS Application	1.4.10
DPT4 Hardware Components
	PLD Configuration	1.4.0
	Host FPGA Configuration	1.4.5
	Expansion FPGA Configuration	1.4.1
DPT5 & DPT6 Hardware Components
	CPLD Configuration	1.5.5
	FPGA Configuration	1.5.10

Known Issues

The following issues are known to exist in this release:
• The 64-bit Windows device driver does not yet support expansion modules or the "virtual serial port" feature.

• The data buffers in the dual-port memory on DPT4 boards can overflow as channels are being started. The overflow can corrupt data for a channel whose buffer is using an adjacent area of the dual-port memory. The problem only occurs when a channel is being started and only occurs on DPT4 boards, not DPT5 or DPT6 boards.

  A suitable work-around for applications that open all their channels at start-up is to wait for all channels to be opened and then flush receive channels before using received data.

• Large amounts of channel data being written to the transmit buffers can saturate the board's local bus, preventing the MIPS processor from obtaining access to the board's local bus long enough to miss buffer interrupts. This has been known to cause corruption of transmitted data and timeout errors reported by the dpchantest diagnostic program. The problem mostly appears on fast systems that are capable of downloading data fast enough to cause the local bus to saturate.

  The only work-around at this time is for applications to limit the rate at which they write data to transmit channels. The suggested limit is an aggregate download rate to approximately 24 Mbytes per second or, assuming all E1 channels are being used,

• Switching to non-blocking I/O mode using the pci_chan_blocking function does not work in all cases for channels that are initially opened with blocking mode. The issue may be dependent on the host operating system as well as other factors. The pci_chan_blocking appears to be able to switch back and forth for channels opened initially with non-blocking mode.

• On rare occasions, DPT5 and DPT6 boards have been known fail to complete a channel DMA transfer. To date, this issue has only been seen on some older desktop systems when multiple boards are running our burn-in tests. A method for detecting possible causes have been added to the FPGA and diagnostic programs.

• Some DPT5 and DPT6 boards may fail to configure the host FPGA when the system is first powered on. This problem has been resolved with a modification to the board (DPT5 rev 0.6 or higher, DPT6 rev 0.4 or higher) and a CPLD configuration update (version 1.5.4 or higher). Contact CAC for updates to boards that exhibit this problem.

• On rare occasions a DPT4 board can hang during the initialization process. This has only been known to occur when being initialized the first time following a power cycle.