December 20, 2001

Overview

Release 3.4.5 of the Empack software includes Version 3.4.5 of the host libraries and Version 3.4.5 of the Embedded Firmware and FPGA configurations.

The following changes are introduced in this release:

• New macro for reading EMC12 status registers.

• Modified EmInitModule to set default DSP clock frequency.

• Added reboot option to eminit program.

• Fixed the verify mode in the emflash program.

• New and modified diagnostic programs.

• New version of Empack embedded code.

• New version of EMC12 FPGA configuration.

Note:

This release includes new embedded code and a new FPGA configuration for EMC12 mezzanines. Customers should run the emflash utility after installation.

New Macro for Reading EMC12 Status Registers

The new macro, EM_CS4231_CSR, allows the EmReadReg function to access the Codec Control & Status Registers in the FPGA on EMC12 modules. There is a CCSR register for each Codec on the EMC12 and the EmReadReg function will access the register for the Codec referenced by the resource handle passed to it.

The information in each CCSR includes the following:

Bit(s)	Meaning
0	ADC is set for 16-bit conversion
1	DAC is set for 16-bit conversion
2	Sample rate is set at 16 KHz
3	Sample rate is set at 32 KHz
4	Sample rate is set at 48 KHz
5	Codec clock is locked to TDM frame
6-15	reserved

The primary purpose for reading the CCSR in an application program is to determine if the Codec clock is locked by checking the value of bit 5. This is used in the new versions of the emfft and emscp diagnostic programs.

Modified EmInitModule to Set Default DSP Clock Frequency

The EmInitModule library function now sets the default DSP clock frequency for EM6X32C mezzanines and EMC12 mezzanines populated with a DSP32C chip.

The default clock frequency is determined by the value stored on the EEROM of the mezzanine (74 MHz for most mezzanines). The embedded code sets the default frequencies when the Empack first powers up. However, if an application changed the setting, it was not previously reset when the mezzanine was next initialized.

Note that calling the EmInitEmpack function calls EmInitModule for each mezzanine detected. So the EmInitEmpack function will also cause the DSP clock frequencies to be reset to the default settings.

Added Reboot Option to Eminit Program

The eminit program has a new -r option that will reboot the embedded code and reconfigure the FPGAs on the designated Empacks. This action may be required if the Empack(s) somehow get into a hung state. For this to work, the Empack(s) must still be accessible via SCSI.

Fixed the Verify Mode in the Emflash program

The verify mode (-v option) for emflash now properly reads and compares the data from the flash memory with the data form the flash object file.

New and Modified Diagnostic Programs

The emtdmfifo program is a new diagnostic that tests the TDM Fifo memory on EM6X32C, EMC12 and EMPCI mezzanines. It tests the Fifos by loading test data into arrays and then transferring them to and from the mezzanines as if it was TDM map data. This test has been used to help diagnose problems with TDM related failures.

The emdiag and emburn programs are modified to incorporate the new emtdmfifo program in their test suites.

The emdiag program has been fixed to disable C12-to-C12 cross-loopback tests specified in a configuration file if the use says the loopback adapters are not installed, to initialize Empacks after both framer tests and to be able to read DOS-format configuration files when run on Solaris.

The emscp program has the following new options:

-d	dsp	- specify the starting DSP for channel mapping
-O	bus	- specify the TDM bus used for outgoing audio data
-I	bus	- specify the TDM bus used for incoming audio data
-L	dB	- specify the input gain for the codecs

The -O and -I options may be used to help determine if problems are related to specific TDM busses. The -d options may be used to help determine if problems are related to a specific DSP. The -L option provides some additional test capability for this program.

The emfft program has the following new options to help determine the cause of problems:

-b	bus	- specify the first TDM bus used for mapping audio data onto TDM
-C		- run tests continuously
-d	dsp	- specify the fist DSP used when mapping DSPs to Codec channels
-i	num	- specify a number of test iterations to run
-l	num[:num]	- specify level set or sets to test

The -b and -d options may be used to help determine if errors are related to specific TDM busses or DSPs. The -i and -C options may be used to run prolonged test cycles. The -l option may be used to test specific settings for input and output levels on the codecs.

Both the emfft and emscp programs are modified to check for proper Codec initialization and frame lock before beginning the audio data transfers.

The DSP program for the emfft diagnostic, dspemfft, has been modified to decrease the amount of glitching on the codec outputs when the sample rate or conversion mode is changed.

The empiomem program now has a -I option which has it test only the internal memory on DSPs. This option is used to help narrow down the cause of detected errors.

New Version of Empack Embedded Code

The new version of the embedded coded, in the flash file fld345.bin, fixes the error handling for several EMC12 access operations. Response timeouts are shortened and error codes are returned.

These changes do not affect the normal operation of the host API functions but provide improved error handling in cases when the EMC12 is malfunctioning.

New Version of EMC12 FPGA Configuration

The FPGA configuration for the EMC12 mezzanine is redesigned to avoid some possible timing problems and to improve synchronization between the Codec chips and the TDM subsystem. The new FPGA configuration also contains logic for an experimental test mode that loops the digital data sent to the codecs back to the digital inputs. The new configuration data is included in the flash file, fpga345.bin.

These changes were made in response to timing differences encountered with a recent production run of EMC12 mezzanines. EMC12 mezzanines from that run are being shipped on Empacks that already include this new FPGA configuration in their flash memory.