Version 1.4.4 of the V6M6 host software and FPGA configurations includes the following changes:

• Support for new DM4C51 module subtypes,
• Added TDM Configurator support for the IMG726 module,
• Burst transfer capability added to the PM4600/PM4700 module.
• Rare problem solved in the VME interface.

Note: This release includes new flash files for FPGA configuration. Please be sure to run pciflashup after installing the software.

New DM4C51 Module Subtypes

The following module types for the DM4C51 are now supported:

PCI_DM4C51

This is the standard DM4C51 module with 128K of external memory partitioned as 64K for program and 64K for data.

PCI_DM4C51_JTAG

A DMC451 module with a JTAG header installed for program debugging.

PCI_DM4C51_64K

A DM4C51 module with 64K of external unified memory (program and data reside in a single memory segment).

PCI_DM4C41_64K_JTAG

A DMC451 module with 64K of unified memory and JTAG header installedfor program debugging.

Note that for the 64K modules, memory address bit 16 is pulled up so when linking your code, both program and data must be placed in SRAM1 bank. This does not effect the C51 memory address since it can only address 64K external, but is used by the host library to determine which bank of memory to load and resolve address labels properly.

Data space must account for the first 0x800 words reserved by the C51.

Below is an example of a 128K linker file for the C51:

/****************************************************************/
/* TI C51 linker command file for DSP Module 4 C51 Board (128K) */
/****************************************************************/
-c                            /* Link using C Conventions       */
-v0                           /* Generate Version 0 COFF format */
-w                            /* Generate Warnings              */
-stack 0x100                  /* 256 Stack                      */
-heap  0x2002                 /* 8194 Heap - Size to allocate   */ 
                              /* one 4095 dma buffer            */
-lc51int00.obj                /* must be before run-time lib.   */
-lrts50.lib                   /* Run-time Support               */

MEMORY
{
  PAGE 0: VECT:   o = 0x0000,  l = 0x30    /* Interrupt Vectors */
          SRAM0:  o = 0x0030,  l = 0xffd0  /* 64K words         */

  PAGE 1: SRAM1:  o = 0x10800, l = 0xf660  /* 64K words         */
          STACK:  o = 0x1fe60, l = 0x0100  /* Stack Space       */
}

SECTIONS
{
  vectors: {c51int00.obj(.vect)} > VECT PAGE 0  /* Vector Table        */
  .boot:   {c51int00.obj(.text)} > SRAM0 PAGE 0 /* Startup code in mem */
  .cinit:  > SRAM0 PAGE 0                   /* Initialization Tables   */
  .text:   > SRAM0 PAGE 0
  .switch: > SRAM0 PAGE 0                   /* Switch Statement Tables */
  .data:   > SRAM0 PAGE 0                   /* Assembly Language Const */
  .const:  > SRAM1 PAGE 1                   /* Constants               */
  .bss:    > SRAM1 PAGE 1, block = 0x80, fill = 0
  .sysmem: > SRAM1 PAGE 1                   /* Dynamic Memory          */
  .stack:  > STACK PAGE 1                   /* System Stack            */
}

Below is an example of a 64K linker file for the C51:

/******************************************************************/
/* TI C51 linker command file for DSP Module 4 C51 Board (64K)    */
/* configurated with a 64 Kword unified Program/Data Memory Space */
/******************************************************************/
-c                              /* Link using C Conventions       */
-v0                             /* Generate Version 0 COFF format */
-w                              /* Generate Warnings              */
-stack 0x100                    /* 256 Stack                      */
-heap  0x2002                   /* 8194 Heap - Size to allocate   */ 
                                /* one 4095 dma buffer            */
-lc51int00.obj                  /* must be before run-time lib.   */
-lrts50.lib                     /* Run-time Support               */

MEMORY
{
  PAGE 0: VECT:   o = 0x10000, l = 0x30    /* Interrupt Vectors   */
          SRAM1:  o = 0x10800, l = 0xf660  /* 64K words           */
          STACK:  o = 0x1fe60, l = 0x0100  /* Stack Space         */
}

SECTIONS
{
  vectors: {c51int00.obj(.vect)} > VECT PAGE 0  /* Vector Table        */
  .boot:   {c51int00.obj(.text)} > SRAM1 PAGE 0 /* Startup code in mem */
  .cinit:  > SRAM1 PAGE 0                   /* Initialization Tables   */
  .text:   > SRAM1 PAGE 0
  .switch: > SRAM1 PAGE 0                   /* Switch Statement Tables */
  .data:   > SRAM1 PAGE 0                   /* Assembly Language Const */
  .const:  > SRAM1 PAGE 0                   /* Constants               */
  .bss:    > SRAM1 PAGE 0, block = 0x80, fill = 0
  .sysmem: > SRAM1 PAGE 0                   /* Dynamic Memory          */
  .stack:  > STACK PAGE 0                   /* System Stack            */
}

The TDM Configurator now supports two operations for IMG726 modules:

1. Values to be loaded in the BT8110 control registers may be specified.
2. TDM source and destination mappings may be automatically generated.

The new BT keyword and its parameters, in the TDM description file, specify these operations:

BT mod enc=val:DS#,# dec=val:DS#,#

where:

• mod is a letter specifying the module location.
• enc and dec specify parameters for PCM or ADPCM encoding or decoding.
• val specifies the value to be loaded into the BT8110's encoding or decoding control registers.
• D is a letter from a to d specifying the TDM bus to be used for TDM destination mappings (serial data into the BT8110).
• S is a letter from a to d specifying the TDM bus to be used for TDM source mappings (serial data out of the BT8110).
• # (a comma separated pair of numbers) specify the first and last data channels to be mapped to the TDM busses.

The BT parameter line must appear before any TDM slot definitions int the TDM description file.

The TDM Configurator will load the BT8110 registers during board intialization. The TDM connections are mapped after the remainder of the description file is parsed. Each channel's input and output to and from the BT8110 chips are mapped onto the correct TDM time slots.

The new version of the PM4600/PM4700 FPGA configuration (pm460025.mcs) provides the capability of performing burst transfers to and from the FIFOs for TDM data.

This feature will be used in a forthcoming version of the WM Kernel.

The new versions of the V6M6 VME interface FPGA configurations (vmepcia41.mcs and vmepcib107.mcs) fix a rare problem in the detection of VME Interrupt Acknowledge cycles.

The problem was that some VME boards assert a glitch on their IACKOUT/ signal at the end of an IACK cycle they respond to. If this would occur on a board upstream in the IACK chain from a V6M6 with a pending interrupt, the V6M6 could interpret the glitch as a valid IACK cycle and think it s interrupt had been acknowledged.