May 28, 1999

Overview

Version 1.8.2 of the V6M6 software and FPGA configurations includes the following changes:

• Enhancements to the pciinit program.

• Modification to the IM2E1 and IM2T1 clock detection logic.

• Fixed executable verification for DM12C549 modules.

• Modification to the pcichip diagnostic program.

Note: This release includes new flash files for FPGA configurations. Be sure to run pciflashup after installing the software.

Enhancements to the pciinit Program

The pciinit program is modified to operate faster and to be able to use DSP processors to clear global memory.

When more than one V6M6 is being initialized the program spawns copies of itself to perform the initialization procedure concurrently on all the boards. If, for some reason, this is undesirable, the spawning (or forking) of separate processes can be disabled by using the new -F option. Note: the process spawning is not implemented for VXWORKS.

The program is now able to use a DSP on a DM2C31, DM4C51 or DM12C549 module to clear global memory when the -Z option is used. This means that global memory may now be initialized on V6M6 boards without MIPS modules and without the host having to do download zeros. The pciinit program chooses the best processor (MIPS or DSP) for clearing global memory.

The software release includes new DSP executables used to clear global memory which are stored in the $CAC/lib directory.

The pciinit program is also modified so that it will not display its start-up banner when using the -r and all options and no V6M6 boards are found.

Tips for further speeding up of the V6M6 initialization process:

• If it is unlikely that new module types will be added to the V6M6 boards in your system, use the -f option to disable checking of the V6M6 flash. The -f option may be added to the invocation of pciinit in the system startup scripts (/etc/init.d/pciinit on Solaris 2.x or towards the end of /etc/rc.local on SunOS 1.4.x).

• Avoid using the -R option unless it is necessary. Performing a hard-reset requires re-configuration of the FPGAs on the V6M6 base board adding at least 7 seconds to the initialization process and several more seconds depending on the types of modules installed. The -R option should never be required when pciinit is run from the system startup scripts.

Modification to the IM2E1 and IM2T1 Clock Detection Logic

In some situations, where the relative clock rates of two incoming E1 or T1 signals are very close and wavering, the faster-clock detection logic may cause occasional loss of data (slips occur in the wrong direction). To avoid this loss of data, revision 17 or higher of the IM2E1 and IM2T1 FPGA configuration (imtelco17.mcs) includes logic to adjust the resulting TDM clock by approximately +3.8 PPM. This is now the default mode when the TDM clock is configured to be derived from the faster RCLK. The TDM clock running slightly faster than the faster RCLK will result in occasional repeated frames from both framers.

In case this mode is not desirable it may be disabled using a new value, 4, as the select argument to the im2e1_rcv_clk or im2t1_rcvclk library functions. The values for the select argument are now defined as:

     0   TDM clock is not generated from the module
     1   TDM clock is derived from RCLK-A
     2   TDM clock is derived from RCLK-B
     3   TDM clock is derived from the faster of
         RCLK-A and RCLK-B and adjusted by +3.8 PPM
     4   TDM clock is derived from the faster of
         RCLK-A and RCLK-B with no adjustment.

A similar change is made to the pci_tdm_timing function so that when an IM2E1 or IM2T1 module is selected as the TDM clock source the value passed in the clksrc argument may be used to disable the adjusted TDM clock mode. The clksrc value for an IM2E1 or IM2T1 module is

     TDM_MODCLK(n) + d

where n is the V6M6 module number (0 - 5) and d is:

     0   TDM clock is derived from RCLK-A
     1   TDM clock is derived from RCLK-B
     3   TDM clock is derived from the faster of
         RCLK-A and RCLK-B and adjusted by +3.8 PPM
     4   TDM clock is derived from the faster of
         RCLK-A and RCLK-B with no adjustment.

The TDM clock source is similarly specified in a TDM configuration file to be used with the pcitdmconfig program. In a TDM configuration file the clock source is defined as follows:

     CLOCK_SRC = modmd

where m is the module resource letter (a - f) and d is defined as above.

Fixed Executable Verification for DM12C549 Modules

The pci_verify_code library function is fixed to verify the downloaded code for DM12C549 modules. In addition, if the DM12C549 broadcast resource is used, the function now checks the code for each of DSPs on the module.

PCICHIP Diagnostic Program Modification

A minor cosmetic change is made to the pcichip diagnostic so that, in most cases, status information will fit on a single line.